The Week In Review: Design


Tools Mentor unveiled new formal-based technologies in the Questa Verification Solution. It offers formal-based RTL-to-RTL equivalence checking flows optimized for verification of manual low-power clock gating, bug fix and ECO validation, and ISO 26262 safety mechanism verification, which the company says which can reduce verification turnaround time by 10X. The app also offers expanded cloc... » read more

The Week In Review: Design


Tools ProPlus Design Solutions unveiled its 9812DX wafer-level 1/f noise characterization system, an enhanced version of its de facto standard 9812D. It includes a more than 10X increase in system resolution, as well as a speedup boost three-to-five times faster than previous systems, higher voltage support up to 200V, and lower current support down to 0.1nA. It also adds a wider range of me... » read more