Power Limits Of EDA

Power has become a major gating factor in semiconductor design. It is now the third factor in design optimization, along with performance, and is almost becoming more important than area. But there are limits to the amount of help that [getkc id="7" kc_name="EDA"] can provide with [getkc id="106" kc_name="power optimization"]. Power is not just an optimization problem. It is a design problem... » read more

Microarchitecture Design For Low Power

As designs move to finFET process nodes, dynamic power reduction has become a requirement. Designers have to eliminate or minimize all sources of redundant switching activity in order to reduce dynamic power in the design. In our last blog, we looked at dynamic power wastage due to redundant adders and multipliers and how to gate these operators to save power. We also mentioned a couple of m... » read more