10nm FinFET Market Heats Up

The 10nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes. Not long ago, Intel announced its 10nm finFET process, with plans to ramp up the technology in 2017. Then, TSMC recently introduced its 10nm process, with plans to move into production by the fourth quarter of 2016. Now, Samsung Electronics said that it has commenced mass... » read more

The Week In Review: Manufacturing

Chipmakers The finFET market is heating up. GlobalFoundries, Intel, Samsung and TSMC are ramping 16nm/14nm finFETs. And 10nm and 7nm finFETs are in the works. The market will shortly have a new competitor—Taiwan’s United Microelectronics Corp. (UMC). Some years ago, UMC licensed finFET technology from IBM. UMC has been a bit quiet about the 14nm finFET technology, but it has made si... » read more

Fins And Wires – How Do We Get To 5nm?

As the industry moves beyond 10nm to the 7nm and 5nm nodes, fundamental shifts are needed to address scaling challenges. Among the priority concerns driving industry changes, particularly with respect to materials and architecture, is the impact on transistor performance from rising parasitic resistance and parasitic capacitance or RC. I spoke about this industry dilemma recently at the SEMICON... » read more

What Transistors Will Look Like At 5nm

Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node. But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. The... » read more

Optical Metrology Solutions For 10nm Films Process Control Challenges

By Sridhar Mahendrakar (a), Alok Vaida (a), Kartik Venkataraman (b), Michael Lenahan (a), Steven Seipp (a), Fang Fanga (a), Shweta Saxena (a), Dawei Hu (b), Nam Hee Yoon (b), Da Song (b), Janay Camp (b), Zhou Ren (b). [a: GlobalFoundries; b:KLA-Tencor] Controlling thickness and composition of gate stack layers in logic and memory devices is critical to ensure transistor performance meets r... » read more

Designing SoC Power Networks

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

Atomic Layer Etch Heats Up

The atomic layer etch (ALE) market is starting to heat up as chipmakers push to 10nm and beyond. ALE is a promising next-generation etch technology that has been in R&D for the last several years, but until now there has been little or no need to use it. Unlike conventional etch tools, which remove materials on a continuous basis, ALE promises to selectively and precisely remove targete... » read more

Interconnect Challenges Rising

Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

Next Challenge: Contact Resistance

In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact. Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or conta... » read more

DAC Day Four: Excitement And Risk

One thing that was new to DAC this year, was an art exhibit. These were pieces of artwork related to our industry, such as chip plots, or more abstract ideas based on design data or analyses. They received many more entrants than their wildest dreams and had to choose a winner from over 80 pieces, but the grand prize was won by a 3D model of a finFET by David Freid of Coventor. This piece was ... » read more

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