Battling Fab Cycle Times


The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Changing Direction In Chip Design


Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

What’s Next For Transistors


The IC industry is moving in several different directions at once. The largest chipmakers continue to march down process nodes with chip scaling, while others are moving towards various advanced packaging schemes. On top of that, post-CMOS devices, neuromorphic chips and quantum computing are all in the works. Semiconductor Engineering sat down to discuss these technologies with Marie Semeri... » read more

China Unveils Memory Plans


Backed by billions of dollars in government funding, China in 2014 launched a major initiative to advance its domestic semiconductor, IC-packaging and other electronic sectors. So far, though, the results are mixed. China is making progress in IC-packaging, but the nation’s efforts to advance its domestic logic and memory sectors are still a work in progress. In fact, China has yet to achi... » read more

FinFET And Multi-Patterning Aware Place-And-Route Implementation


The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Nitro-SoC place and route system handles them. To read more, click here. » read more

Choosing Power-Saving Techniques


Engineers have come up with a long list of ways to save power in chip and system designs, but there are few rules to determine which approaches work best for any given design. There is widespread confusion about what techniques should be used where, which IP or subsystem is best, and how everything should be packaged together. The choices include everything from the proper level of clock and... » read more

Reflecting Back On 2016


Anyone can make a prediction, and sometimes the more outlandish they are the more they get noticed. But at the end of the year some people hit the mark while others may have been way off. Many people simply make projections based on the current trajectory of trends, while others look for the potential discontinuities that may lie ahead. Semiconductor Engineering examines the projections made... » read more

Etching Technology Advances


Let’s get really, really small. That directive from leading semiconductor companies and their customers is forcing the whole semiconductor supply chain to come up with new ways to design and manufacture ever-shrinking dimensions for chips. The current push is to 10nm and 7nm, but R&D into 5nm and 3nm is already underway. To put this in perspective, there are roughly two silicon atom... » read more

Tech Talk: FD-SOI vs. FinFET


Jamie Schaeffer, 22FDX program director at GlobalFoundries, talks about the future of FD-SOI, what the tradeoffs are in performance, power and cost compared with finFETs, how many mask layers and patterning steps are required for each, and when 12nm FD-SOI will be introduced. Related Stories To 7nm And Beyond GlobalFoundries’ top technologists open up on next-gen FD-SOI, the economi... » read more

Timing Closure Issues Resurface


Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

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