7nm Design Success Starts With Multi-Domain Multi-Physics Analysis


Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating volt... » read more

Multi-Patterning Issues At 7nm, 5nm


Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

Can We Measure Next-Gen FinFETs?


After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology. Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yi... » read more

Measuring Atoms And Beyond


David Seiler, chief of the Engineering Physics Division within the Physical Measurement Laboratory at the National Institute of Standards and Technology (NIST), sat down with Semiconductor Engineering to discuss the current and future directions of metrology. NIST, a physical science laboratory, is part of the U.S. Department of Commerce. What follows are excerpts of that conversation. SE: W... » read more

Partitioning For Power


Examine any smartphone design today and most of the electronic circuitry is "off" most of the time. And regardless of how many processor cores are available, it's rare to use more than a couple of those cores at any point in time. The emphasis is shifting, though, as the mobility market flattens and other markets such as driver-assisted vehicles and IoT begin gaining traction. In a car, turn... » read more

Moore’s Law Debate Continues


Does shrinking devices still make sense from a cost and performance perspective? The answer isn’t so simple anymore. Still, the discussion as to whether semiconductors are still on track with [getkc id="74" comment="Moore's Law"] occurs on a frequent enough basis to continue analyzing at least some of the dynamics at play. There is much speculation about what happens after 7nm, as well as ... » read more

FinFET Front-End-of-Line (FEOL) Process Integration With SEMulator3D


Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology inno... » read more

GlobalFoundries Rolls Out 12nm FD-SOI Process


GlobalFoundries uncorked its 12FDX platform, incorporating a 12nm fully-depleted silicon-on-insulator process technology. The foundry’s Fab 1 in Dresden, Germany, will support customer development with the 12nm process, with product tape-outs scheduled for the first six months of 2019. The 12FDX technology follows the company’s 22FDX platform involving a 22-nanometer process. The foundr... » read more

The Real Value Of Digital Horsepower


Chipmakers and systems vendors are beginning to experiment with a slew of new ways to beef up performance and reduce power and area, now that shrinking features no longer guarantees those improvements. The number of new ideas introduced at industry conferences in the past few months is almost mind-boggling. Just on the CPU side there are new architectures that improve the amount of work that... » read more

Noise Killed My Chip


In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed. Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It ... » read more

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