22nm Process War Begins


Many foundry customers at the 28nm node and above are developing new chips and are exploring the idea of migrating to 16nm/14nm and beyond. But for the most part, those companies are stuck because they can’t afford the soaring IC design costs at advanced nodes. Seeking to satisfy a potential gap in the market, [getentity id="22819" comment="GlobalFoundries"], [getentity id="22846" e_name="... » read more

The Evolution Of EUV


EUV systems are beginning to ship to large foundries in volume, setting the stage for one of the biggest leaps in technology the semiconductor industry has ever witnessed. ASML has emerged as the sole supplier in this market, but it has taken an entire ecosystem to develop EUV. It has taken billions of dollars of investment by ASML, along with enormous cash infusions by Intel and TSMC, contr... » read more

Will Self-Heating Stop FinFETs


New transistor designs and new materials don’t appear out of thin air. Their adoption always is driven by the limitations of the incumbent technology. Silicon germanium and other compound semiconductors are interesting because they promise superior carrier mobility relative to silicon. [getkc id="185" kc_name="FinFET"] transistor designs help minimize short channel effects, a critical limi... » read more

The Hunt For A Low-Power PHY


Physics has been on the side of chipmakers throughout most of the lifetime of [getkc id="74" comment="Moore's Law"], but when dealing with the world outside the chip, physics is working against them. Pushing data at ever-faster rates through boards and systems consumes increasing amounts of power, but the power budget for chips has not been increasing. Could chips be constrained by their int... » read more

Managing Voltage Drop At 10/7nm


Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

System-Level Testing


This white paper on system-level testing for semiconductors. Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span of applications: automotive, mobile computing, wearables, and more; Semiconductor trends driving necessary shifts in testing method... » read more

Patterning Problems Pile Up


Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

China: Fab Boom or Bust?


China’s semiconductor industry continues to expand at a frenetic pace. At present there are nearly two dozen new fab projects in China. Whether all these fab projects get off the ground is not entirely clear because the dynamics in China remain fluid. What is clear is the motivation behind this building frenzy—China is trying to reduce its huge trade imbalance in ICs. The country continu... » read more

Power Impacting Cost Of Chips


The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

Battling Fab Cycle Times


The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

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