tag: flip-chip

LAB Flip Chip Reflow Process Robustness Prediction By Thermal Simulation
By Gabriel Chang - 16 Nov, 2023 - Comments: 0

By Gabriel Chang and Ricky Zang Nowadays, there are many interconnects in IC chips. One of the packaging goals is to connect an IC to the next level of subsystem circuitry (package substrates/print circuit boards). Mass reflow (MR) of solder joints is a widely adapted and stable process in the industry. The applications of MR include flip chip, ball mounting, surface mount technology (SMT), ... » read more

Reverse Laser Assisted Bonding (R-LAB) Technology For Chiplet Module Bonding On Substrate
By SeokHo Na - 21 Sep, 2023 - Comments: 0

By SeokHo Na, MinHo Gim, GaHyeon Kim, DongSu Ryu, DongJoo Park, and JinYoung Kim In the recent semiconductor market, there are many applications including smartphone, tablets, central processing units (CPUs), artificial intelligence (AI), data cloud and more that are expecting and experiencing rapid growth. As most of these applications require high performance, single-die Flip Chip packages... » read more

A Flip-Chip, Co-Packaged With Photodiode, High-speed TIA in 16nm FinFET CMOS
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes" was published by researchers at University of Toronto, Alphawave IP, and Huawei Technologies Canada. Abstract: "A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude... » read more

Challenges Grow For Creating Smaller Bumps For Flip Chips
By Anne Meixner - 18 May, 2023 - Comments: 0

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM�... » read more

Next Gen Laser Assisted Bonding (LAB) Technology
By SeokHo Na - 18 May, 2023 - Comments: 0

In the semiconductor market, there are many applications including smartphone, tablets, central processing units (CPUs), artificial intelligence (AI), data cloud and more that are expecting rapid growth. Among them, CPU data processing, AI and data cloud require much higher power consumption than smart phones or tablets. For the higher power applications, Flip Chip ball grid array (FCBGA) or 2.... » read more

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
By Karen Heyman - 11 Oct, 2022 - Comments: 0

Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Fan-Out Packaging Gets Competitive
By Karen Heyman and Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Flip-Chip Integration of a GaSb Semiconductor Optical Amplifier with a Silicon Photonic Circuit
By Technical Paper Link - 01 Jul, 2022 - Comments: 0

New research paper titled "Hybrid silicon photonics DBR laser based on flip-chip integration of GaSb amplifiers and µm-scale SOI waveguides" by researchers at Tampere University (Finland). Abstract: "The development of integrated photonics experiences an unprecedented growth dynamic, owing to accelerated penetration to new applications. This leads to new requirements in terms of functional... » read more

Die-level Thinning and Integrating Route For Singulated MPW Chips Using Both Silicon Sensors and CMOS Devices
By Technical Paper Link - 30 Apr, 2022 - Comments: 0

Abstract "Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an el... » read more

Expanding Advanced Packaging Production In The U.S.
By Mark LaPedus - 05 Jan, 2022 - Comments: 0

The United States is taking the first steps toward bringing larger-scale IC packaging production capabilities back to the U.S. as supply chain concerns and trade tensions grow. The U.S. is among the leaders in developing packages, especially new and advanced forms of the technology that promise to shake up the semiconductor landscape. And while the U.S. has several packaging vendors, North A... » read more

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