Formal Verification’s Continental Divide


Formal verification is picking up steam with engineering groups worldwide doing complex functional verification for bug-free and reliable digital chips. In fact, many difficult verification challenges are solved with formal verification, given its flexibility in targeting a broad range of verification challenges. Recent advances in formal verification’s ease of use and capacity has made it an... » read more

Can Formal Replace Simulation?


A year ago, [getentity id="22147" comment="Oski Technology"] achieved something that had never happened before. It brought together 15 of the top minds in [getkc id="33" kc_name="formal verification"] deployment and sat them down in a room to discuss the problems and issues they face and the ways in which they are attempting to solve those problems. Semiconductor Engineering was there to record... » read more

Rediscovering Coverage Insurance


When coverage comes up in conversation, if it comes up at all, it’s always a matter of car, home or health insurance. Coverage and functional verification are unlikely to be used in that discussion, or any other for that matter. That’s too bad because engineering groups grapple with when is enough verification enough, like some kind of coverage insurance. Oh sure, simulation and emulatio... » read more

10 Ways To Skin A Formal Puzzle


During the holidays, OneSpin issued a challenge to solve the classic Einstein’s Riddle using any formal verification tool. Although this puzzle was meant to be a little holiday fun, its solution required thought and some useful formal techniques applicable in everyday functional verification. We received a broad range of answers from engineers across the globe in different companies, inclu... » read more

Carving Up Verification


Anirudh Devgan, executive vice president and general manager of [getentity id="22032" e_name="Cadence's"] System & Verification Group, sat down with Semiconductor Engineering to discuss the evolution of verification. What follows are excerpts of that conversation. SE: What’s changing in [getkc id="10" kc_name="verification"]? Devgan: Parallelism, greater capacity and multiple engine... » read more

Why Auto Designs Take So Long


Designing chips for the automotive market is adding significant overhead, particularly for chips with stringent safety requirements. On the verification side it could result in an additional 6 to 12 months of work. On the design side, developing the same processor in the mobile market would take 6 fewer man months. And when it comes to complex electronic control units (ECUs) or [getkc id="81... » read more

Find Your Way To San Jose Next Week… For DVCon, Of Course!


If you’re asked “Do you know the way to San Jose?” in the next few days, chances are it’s a newbie to DVCon. Everyone else in chip design verification knows the way to the annual Design and Verification Conference and Exhibition about to convene at the San Jose DoubleTree Hotel. This year’s program is stacking up to be an insightful and educational four days of tutorials, paper ses... » read more

Formal Verification Takes Safety-Critical Applications For A Drive


The high reliability of safety-critical chips for automotive applications is a well-known imperative for today’s higher-end cars and as driverless cars move closer to reality. Uber, in fact, is testing autonomous cars in Boston of all places, where aggressive driving reigns supreme and honking the horn is considered an art form. As automotive manufacturers realize that their differentiatio... » read more

Verification Specialists And Generalists


Step into any weekly status update meeting where the topic is chip design verification, especially if formal verification is on the agenda, and it’s clear the verification department is moving much like traditional corporate environments. That is, there are generalists with loads of knowledge about many different verification tools and techniques and then there are specialists or experts who ... » read more

DVCon Europe: 2 Days Of Verification Presentations To Enthusiastic Attendees


Design verification was on full display last week in Munich, Germany, as DVCon Europe offered two full days of more than 30 sessions. Attendees could choose from 16 tutorials, two panels, three keynotes and 16 technical presentations or wander through a small but active exhibit floor, with exhibitors that included OneSpin. The conference for engineers by engineers is meant to be educational,... » read more

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