tag: formal

Interoperability And Automation Yield A Scalable And Efficient Safety Workflow
By Ann Keffer - 07 Mar, 2024 - Comments: 0

By Ann Keffer, Arun Gogineni, and James Kim Cars deploying ADAS and AV features rely on complex digital and analog systems to perform critical real-time applications. The large number of faults that need to be tested in these modern automotive designs make performing safety verification using a single technology impractical. Yet, developing an optimized safety methodology with specific f... » read more

What’s Required To Secure Chips
By Ed Sperling - 06 Apr, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about how to verify that a semiconductor design will be secure, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketing at Expedera; and Dave Kelf, CEO of Breker Verification. ... » read more

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?
By Joseph Hupcey III - 03 Feb, 2022 - Comments: 0

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero risk of unwanted surprises escaping undetected into your end-product. In order of high-to-low probability, consider: The presence of a weird-yet-entirely-possible corner-case bug Bugs “insid... » read more

Using Symbolic Simulation For SRAM Redundancy Repair Verification
By Hari Sathianathan - 27 Jan, 2022 - Comments: 0

Innovations in Very Deep Sub-Micron technologies, such as the advent of three-dimensional FinFET transistor structures, have facilitated the implementation of very large embedded SRAM memories in System-on-Chip (SoC) designs to the point where they occupy the majority of the chip die area. To get maximum memory capacity on the smallest die area, SRAM bitcells are designed with the minimum possi... » read more

Bug Hunt! Spiraling In On Formal Coverage Closure
By Mark Eslinger - 13 Jan, 2022 - Comments: 0

By Mark Eslinger and Jin Hou Many companies have used formal verification to verify complex SoCs and safety-critical designs. Using formal verification to confirm design functionalities and to uncover functional bugs is emerging as an efficient verification approach. Although formal verification will not handle the complexity of a design at the SoC level, it is an efficient tool to verify th... » read more

Dealing With Market Shifts
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Back in the days when I was in EDA development, I was taken in by the words of Clayton Christensen when he published "The Innovators Dilemma." He successfully introduced the technology world to the ideas of disruptive innovation. One of the key takeaways was that you should always be working to make your own successful products redundant, or someone else will do it for you. One tool I worked... » read more

The Road To Osmosis
By Rob van Blommestein - 27 Oct, 2021 - Comments: 0

It’s happening. Some may have speculated that, with the acquisition of OneSpin by Siemens, the OneSpin user group meeting, more commonly known as Osmosis, would be formally (pun intended) absorbed into a larger Siemens event. Well, I’m here to tell you that Osmosis is officially on the books and will continue to focus on the specific area of formal verification. The team has been working di... » read more

Deep Dive Into Hardware Security Verification At This Year’s Osmosis User Group
By Rob van Blommestein - 19 Oct, 2021 - Comments: 0

We’ve been talking for months about how to successfully verify designs to avoid security weaknesses and vulnerabilities. In the upcoming Osmosis (OneSpin Meeting on Solution, Innovation & Strategy) user group event, attendees will get to hear first-hand from one of our most ardent users how they were able to secure their hardware design. The two-day, virtual event on November 3rd and 4... » read more

Easing The Burden Of Early Bug Detection
By Rob van Blommestein - 26 Aug, 2021 - Comments: 0

Integrated circuit designers are under constant pressure to deliver bug free code that meets ever more rigorous requirements. It is well known that the more bugs that can be detected early in the development process, the faster and easier that development effort will be. However, early bug detection requires a verification overhead on the designer that can be onerous and impact the design proce... » read more

Formally Verifying SystemC/C++ Designs
By Rob van Blommestein - 29 Jul, 2021 - Comments: 0

We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components ... » read more

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