Crossing The Chasm: Uniting SoC And Package Verification


Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, and foundries must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.... » read more

2.5D Surprises And Alternatives


Semiconductor Engineering sat to discuss advanced packaging issues with Juan Rey, senior director of engineering for Calibre at [getentity id="22017" e_name="Mentor Graphics"]; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; and Lisa Minwell, [getentity id="22242" e_name="eSilicon's"] senior director of IP marketing. What follows are excerpts of that conversation. ... » read more

Fan-Out Packaging Gains Steam


Fan-outs are creating a buzz and gaining steam in the market at a pace far beyond what anyone would have expected even at the start of the year. The approach, which has been around for several years, is a wafer-level packaging process that enables ultra-thin, high-density packages. So why the buzz? Apple is apparently moving to [getkc id="202" kc_name="fan-out"] packaging, according to an... » read more