Gaps In Performance, Power Coverage


The semiconductor industry always has used metrics to define progress, and in areas such as functional verification significant advances have been made. But so far, no effective metrics have been developed for power, performance, or other system-level concerns, which basically means that design teams have to run blind. On the plus side, the industry has migrated from the use of code coverage... » read more

Busting The 3 Big Common Myths About Physical Prototyping


FPGA-based prototyping is so popular because it provides an economical way to functionally validate an ASIC design by creating a prototype that runs “at speed”, includes real world I/O, and enables early software development. Experienced prototypers are familiar with its benefits but there are still designers opposed to physical prototyping because they believe that it does not scale to sup... » read more

Hybrid Verification: The Only Way Forward


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

The Week In Review: Design


Tools eSilicon uncorked a GDSII online quote system for TSMC, which allows chipmakers to pick a variety of information ranging from process technology to package to yield and tapeout and production forecast and get a quote within minutes. This is a new twist in the value chain provider market. Synopsys added program to speed up FPGA-based prototype creation, which includes approved third-pa... » read more

New Uses For Emulation


Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

Mythbusting: Co-Design


By Ann Steffora Mutschler It turns out that while there needs to be understanding between hardware and software engineers, the people doing the programming don’t actually want or need to interact. There is not, nor probably ever will be, one single team with hardware and software engineers happily working together on a project. But it’s not a total disconnect. There are a number o... » read more

Experts At The Table: Verification Strategies


By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are ex... » read more

Mixing It Up


By Ann Steffora Mutschler To enable the next level of productivity in the verification space, certain tools need to be combined and integrated in a very meaningful way. The concept is far from new. This happened on the RTL to GDS front between synthesis and place and route. The tools work very closely and there is bi-directional collaboration. It also happened in the functional verification... » read more

Hybrid Prototype Benefits


By Troy Scott This month Nithya asked me to contribute a post on hybrid prototyping and add some color to how design teams have been benefiting from integration between virtual and FPGA-based prototypes. It’s been about six months since Synopsys announced the availability of a data exchange, which links a Virtualizer Development Kit (VDK) to the HAPS FPGA-based prototyping system based on AM... » read more

3 Ways To Differentiate


Time-to-market pressures and complexity have put the squeeze on design teams. They have to bring incredibly complex SoCs to market on time, make sure they’re functionally correct and work within a tight power budget, and they have to come in on or under budget. Amazingly, they’re still able to accomplish this, thanks to some heroic efforts on the part of engineers and some incredible adv... » read more

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