Blog Review: Aug. 19

Several of this week's top reads from Ansys' Justin Nescott sound like they're straight from the pages of sci-fi novels (and comic books). An MIT project is getting close to creating the Iron Man suit, one company plans to finally build a space elevator, and Los Angeles takes an innovative approach to fighting the California drought: 96 million black plastic balls. Smartphones are so yestery... » read more

HDMI 2.0 Design And Verification Challenges

High-Definition Multimedia Interface (HDMI) is an audio/video (A/V) trans- mission protocol, which is omnipresent in consumer electronics, personal computing, and mobile products. Modern-day requirements of big screen resolutions, 3D, and multi-channel/multi-stream audio have pushed display devices to use a completely digital, high-speed transmission media, requiring a multi-layered protocol li... » read more

Fixing Functional Coverage

Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous task—defining the patterns necessary to exercise designs of increasing size. It was successfully argued that spending time writing models instead of creating stimulus and having a computer p... » read more

Know What To Look For

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

Week In Review: System-Level Design

Cadence rolled out a new version of its functional verification platform, greatly improving performance and updating it to deal with the big increases in third-party and re-used IP in designs. For IP and block verification, the company said it increased formal analysis performance by up to 20% and simulation by up to 10 times. The debugger also reduces the database size by 10 times and the time... » read more

When Is Verification Done?

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

Experts At The Table: The Future Of Verification

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Start Verification Early To Avoid Pitfalls Later

It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made. Harry Foster, chief scientist for v... » read more

Where Should I Use Formal Functional Verification?

With innovations in formal technologies and methodology, the benefits of formal functional verification apply in many more areas. Although a generic awareness of where formal functional verification applies is useful, understanding the "what" and the "why" leads to greater success. Clearly, if we understand the characteristics of areas with high formal applicability, we can identify not only wh... » read more

Experts At The Table: Verification Strategies

By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are ex... » read more

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