Week In Review: Semiconductor Manufacturing, Test


SEMICON West returned in force this week, with a focus on AI and deep learning  in semiconductor manufacturing, security, heterogenous ICs, and the march toward a $1 trillion chip market. Lam Research President and CEO, Tim Archer, opened with the keynote presentation. Fig. 1: SEMICON West panel: AI’s influence on growth, China-U.S. trade war, and the importance of climate policy were... » read more

Epi SiGe Application Using METRION In-Line SIMS System


The epitaxial process is a well-established deposition technique in semiconductor fabrication because it enables the ability to achieve much higher doping concentrations than can be obtained via ion implantation. As we move toward <5nm technology, a key process for enabling gate-all-around FET (GAAFET) is the stacked multi-lattice of Silicon (Si) and Silicon-germanium (SiGe) epi process for ... » read more

Using More Germanium In Chips for Energy Efficiency & Achievable Clock Frequencies


A new technical paper titled "Composition Dependent Electrical Transport in Si1−xGex Nanosheets with Monolithic Single-Elementary Al Contacts" was published by researchers at TU Wien (Vienna University of Technology), Johannes Kepler University, CEA-LETI, and Swiss Federal Laboratories for Materials Science and Technology. Find the technical paper here. Published September 2022. Abstrac... » read more

Improved graphene-base heterojunction transistor with different collector semiconductors for high-frequency applications


New research paper from TU Dresden & others. Abstract "A new kind of transistor device with a graphene monolayer embedded between two n-typesilicon layers is fabricated and characterized. The device is called graphene-base heterojunction transistor (GBHT). The base-voltage controls the current of the device flowing from the emitter via graphene to the collector. The transit time for e... » read more

5/3nm Wars Begin


Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

5nm Vs. 3nm


Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

System Bits: April 30


Future batteries could use a graphene sponge Researchers at Sweden’s Chalmers University of Technology devised a porous, sponge-like aerogel, made of reduced-graphene oxide, to serve as a freestanding electrode in the battery cell. This utilization has the potential to advance lithium sulfur batteries, which are said to possess a theoretical energy density about five times greater than lithi... » read more

Can Graphene Be Mass Manufactured?


Since the isolation of graphene in 2004, the high mobility and unique transport properties of 2-dimensional semiconductors have tantalized physicists and materials scientists. Their in-plane carrier transport and lack of dangling bonds potentially can minimize line/edge scattering and other effects of extreme scaling. While 2-D materials cannot compete with silicon at current device dime... » read more

Silicon’s Long Game


The era of all-silicon substrates and copper wires may be coming to an end. Progress in the future increasingly depends on more exotic combinations of materials that are developed for specific applications. But after years of predicting the death of silicon, it appears those predictions may be premature. That's not always obvious, given the growing number of chemical combinations being creat... » read more

Managing Parasitics For Transistor Performance


The basic equations describing transistor behavior rely on parameters like channel doping, the capacitance of the gate oxide, and the resistance between the source and drain and the channel. And for most of the IC industry's history, these have been sufficient. “Parasitic” or “external” resistances and capacitances from structures outside the transistor have been small enough to discoun... » read more

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