tag: GPU acceleration

A Safety Island For Safe Use of HPC Devices For Safety-Critical Systems with RISC-V
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains” was published by researchers at Barcelona Supercomputing Center and Intel. Abstract: "HPC (High Performance Computing) devices increasingly become the only alternative to deliver the performance needed in safety-critical autonomous systems (e.g., autonomous cars, unmanned planes) du... » read more

Combination of AI Techniques To Find The Best Ways to Place Transistors on Silicon Chips
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "AutoDMP: Automated DREAMPlace-based Macro Placement" was published by researchers at NVIDIA. Abstract: "Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design power-performance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated place... » read more

Getting Ready For EUV
By Jan Willis - 06 Sep, 2017 - Comments: 0

The highly anticipated introduction of extreme ultra-violet (EUV) lithography is reflected in recent surveys conducted by the eBeam Initiative, which will be presented on Sept. 11 at the annual Photomask Technology Symposium in Monterey, Calif.  There are many changes are coming to the mask industry, in addition to EUV. Those include greater use of inverse-lithography technologies (ILT) and... » read more

The Secret Life Of Accelerators
By Ed Sperling - 27 Jul, 2017 - Comments: 0

Accelerator chips increasingly are providing the performance boost that device scaling once provided, changing basic assumptions about how data moves within an electronic system and where it should be processed. To the outside world, little appears to have changed. But beneath the glossy exterior, and almost always hidden from view, accelerator chips are becoming an integral part of most des... » read more

Inside Lithography And Masks
By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

Big Changes In Patterning
By Ed Sperling - 22 Feb, 2017 - Comments: 0

Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], sat down with Semiconductor Engineering to discuss patterning issues at 10nm and below, including mask alignment, the need for GPU acceleration, EUV's future impact on the total number of masks, and what the re-introduction of curvilinear shapes will mean for design. SE: Patterning issues are getting a lot of attention at 10nm and 7n... » read more

Will GPU-Acceleration Mean The End Of Empirical Mask Models?
By Ryan Pearman - 20 Oct, 2016 - Comments: 0

Shrinking mask feature sizes and increasing proximity effects are driving the adoption of simulation-based mask processing. Empirical models have been most widely used to date, because they are faster to simulate. Today, GPU-acceleration is enabling fast simulation using physical models. Does the ability of GPU-acceleration to make physical models a practical solution mean the end of empirical ... » read more

Tech Talk: GPU-Accelerated Photomasks
By Ed Sperling - 22 Mar, 2016 - Comments: 0

Noriaki Nakayamada, group manager for the data control engineering group in NuFlare's Mask Lithography engineering Department, talks about what's changing on the mask side, where the trouble spots are, and how to deal with them at advanced process nodes. [youtube vid=f8PixJMadXw] » read more

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