Data Buffering’s Role Grows


Data buffering is gaining ground as a way to speed up the processing of increasingly large quantities of data. In simple terms, a data buffer is an area of physical [getkc id="22" kc_name="memory"] storage that temporarily stores data while it is being moved from one place to another. This becomes increasingly necessary in data centers, autonomous vehicles, and for [getkc id="305" kc_name=... » read more

Blog Review: Jan. 10


Rambus' Aharon Etengoff explains the Meltdown and Spectre CPU vulnerabilities and why they could negatively affect the semiconductor industry for decades. Cadence's Paul McLellan has an explainer on Meltdown and how it's an unintended consequence of a processor behaving as intended. Mentor's Ruben Ghulghazaryan and Jeff Wilson investigate using machine learning to predict post-deposition ... » read more

Advanced ASICs: It Takes An Ecosystem


I remember the days of the IDM (integrated device manufacturer). For me, it was RCA, where I worked for 15 years as the company changed from RCA to GE and then ultimately to Harris Semiconductor. It’s a bit of a cliché, but life was simpler then, from a customer point of view at least. RCA did it all. We designed all the IP, did the physical design, owned fabs, assembly and test facilities a... » read more

New Drivers For I/O


Interface standards are on a tear, and new markets are pushing the standards in several directions at the same time. The result could be a lot more innovation and some updates in areas that looked to be well established. Traditionally, this has been a sleepy and predictable part of the industry with standards bodies producing updates to their interfaces at a reasonable rate. Getting data int... » read more

Can A Supply Chain Be Too Efficient?


The semiconductor industry is a model of efficiency—literally. When other industries look at adding smart manufacturing into their operations, they often look to chip manufacturing as a shining example. After decades of business gyrations, semiconductor companies have figured out how to instill efficiency into every aspect of making chips. This is evident in device scaling. At 90nm, the co... » read more

Start Your HBM/2.5D Design Today


High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. In June 2015, AMD introduced its Fiji processor, the first HBM 2.5D design, which comp... » read more

Shrink Or Package?


Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

The Hunt For A Low-Power PHY


Physics has been on the side of chipmakers throughout most of the lifetime of [getkc id="74" comment="Moore's Law"], but when dealing with the world outside the chip, physics is working against them. Pushing data at ever-faster rates through boards and systems consumes increasing amounts of power, but the power budget for chips has not been increasing. Could chips be constrained by their int... » read more

HBM Upstages DDR In Bandwidth, Power


For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

HBM2: It’s All About The PHY


HBM DRAM is currently used in graphics, high-performance computing (HPC), server, networking and client applications. HBM, says JEDEC HBM Task Group Chairman Barry Wagner, provides a “compelling solution” to reduce the IO power and memory footprint for the most demanding applications. Recent examples of second-generation HBM deployment include NVIDIA’s Quadro GP100 GPU which is paired wit... » read more

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