Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP


Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication bet... » read more