High-Performance Memory Challenges


Designing memories for high-performance applications is becoming far more complex at 7/5nm. There are more factors to consider, more bottlenecks to contend with, and more tradeoffs required to solve them. One of the biggest challenges is the sheer volume of data that needs to be processed for AI, machine learning or deep learning, or even in classic data center server racks. “The design... » read more

Toward High-End Fan-Outs


Foundries and OSATs are working on more advanced fan-outs, including some with vertically stacked die inside the package, filling a middle ground between lower-cost fan-outs and systems in package on one side and 2.5D and 3D-ICs on the other. These new [getkc id="202" kc_name="fan-outs"] have denser interconnects than previous iterations, and in some cases they include multiple routing layer... » read more

The Hunt For A Low-Power PHY


Physics has been on the side of chipmakers throughout most of the lifetime of [getkc id="74" comment="Moore's Law"], but when dealing with the world outside the chip, physics is working against them. Pushing data at ever-faster rates through boards and systems consumes increasing amounts of power, but the power budget for chips has not been increasing. Could chips be constrained by their int... » read more

HBM2: It’s All About The PHY


HBM DRAM is currently used in graphics, high-performance computing (HPC), server, networking and client applications. HBM, says JEDEC HBM Task Group Chairman Barry Wagner, provides a “compelling solution” to reduce the IO power and memory footprint for the most demanding applications. Recent examples of second-generation HBM deployment include NVIDIA’s Quadro GP100 GPU which is paired wit... » read more

2.5D Adds Test Challenges


OSATs and ATE vendors are making progress in determining what works and what doesn't in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology. A [getkc id="82" kc_name="2.5D"] package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an [getkc id="204" kc_name="interposer"] or some type of silicon bri... » read more

The Challenges Of Designing An HBM2 PHY


Originally targeted at the graphics industry, HBM continues to gain momentum in the server and networking markets as system designers work to move higher bandwidth closer to the CPU. Expanding DRAM capacity – which boosts overall system performance – allows data centers to maximize local DRAM storage for wide throughput. HBM DRAM architecture effectively increases system memory bandwidth... » read more

Performance Increasingly Tied To I/O


Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

Smart Manufacturing Gains Momentum


Smart manufacturing is gaining traction as a way of addressing increased market fragmentation while still leveraging economies of scale. The goal is to add a level of flexibility into manufacturing processes that until recently was considered impossible. Although the approach makes sense in theory, real-world implementation is proving far from consistent. Sometimes referred to as Industr... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of tha... » read more

Architecting Memory For Next-Gen Data Centers


The industry’s insatiable appetite for increased bandwidth and ever-higher transfer rates is driven by a burgeoning Internet of Things (IoT), which has ushered in a new era of pervasive connectivity and generated a tsunami of data. In this context, datacenters are currently evaluating a wide range of new memory initiatives. All seek to optimize efficiency by reducing data transport, thus sign... » read more

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