Getting The Power/Performance Ratio Right

Getting to market quickly means determining as soon as possible if a concept for a new design will work or not, particularly where power and performance are concerned. Making this determination requires intimate knowledge of the scenarios in which the device will operate — and that is just the start. In order to set things up, you need to somehow model the system, which could be done in a ... » read more

How High-Level Synthesis Was Used To Develop An Image-Processing IP Design From C++ Source Code

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

The Secret to Reaching Rapid Verification Closure

Every design team is looking to reduce RTL verification time in order to meet aggressive schedules. Successful teams have moved their level of design abstraction up to the C++ or [gettech id="31018" comment="SystemC"] level and employ [getkc id="105" comment="high-level synthesis"] (HLS) within their design flow. By taking advantage of this high-level description, these teams also plug into int... » read more

ESL Flow is Dead

It was 20 years ago that Gary Smith coined the term [getkc id="48" comment="Electronic System Level"] (ESL). He foresaw the next logical migration in abstraction up from the [getkc id="49" comment="Register Transfer Level"] (RTL) to something that would be capable of describing and building complex electronic systems. He also saw that the future of EDA depended upon who would control that marke... » read more

C-Based SoC Design Flow And EDA Tools

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC’s complexity and the timing closure caused by deep submicron technology. To solve these two problems, we propose a C-based SoC design environment t... » read more

ESL: 20 Years Old, 10 To Go

It is a common perception that the rate of technology adoption accelerates. In 1873, the telephone was invented and, after 46 years, it had been adopted by one-quarter of the U.S. population. Television, invented in 1926 took 26 years. The PC in 1975 took just 16 years. It took only 7 years after the introduction of the Internet in 1991 before it was seeing significant levels of adoption. So... » read more

Mentor Buys Remainder Of Calypto

Back in 2002, a small startup company decided to tackle one of the most difficult problems in EDA—one that, if solved, could have opened up a whole new level of abstraction. Back when [getkc id="29" kc_name="logic synthesis"] was the new tool to try out, it suffered from the fact that gate-level [getkc id="11" kc_name="simulation"] had to be performed on the output, even if the input had been... » read more

Tale Of Two HLS Viewpoints

The Design Automation Conference attracts several co-located conferences, symposiums and other such gathering of people, often on more specialized topics than would appeal to the general DAC attendees. Some of them are more research-focused, but one conference is somewhat strange in that it is about a subject that has transitioned to commercial tool development and yet still remains an active a... » read more

Problems Ahead For EDA

You may have discovered that the Semiconductor Engineering Knowledge Center (KC) provides various ways in which data can be viewed. One way is to see what events happened in a given year. During the 1990s, company activity in terms of new startups and acquisitions reached a peak, and in 1997 there were at least 29 startups that the KC contains and 25 companies acquired (let us know if there wer... » read more

Does Fast Simulation Help Debug Productivity?

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

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