tag: high-level synthesis

Designing for FPGA Accelerators
By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This research paper titled "High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks" was published by researchers at Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy). According to the paper's abstract, "This paper presents a survey ... » read more

Heterogeneous Redundant Circuit Design Approaches for FPGAs
By Technical Paper Link - 12 Jul, 2022 - Comments: 0

New research paper titled "Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs" from researchers at Nagasaki University. Abstract (Partial) "In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach foc... » read more

Toward Democratized IC Design And Customized Computing
By Jason Cong - 28 Jun, 2022 - Comments: 0

Integrated circuit (IC) design is often considered a “black art,” restricted to only those with advanced degrees or years of training in electrical engineering. Given that the semiconductor industry is struggling to expand its workforce, IC design must be rendered more accessible. The benefit of customized computing General-purpose computers are widely used, but their performance improv... » read more

High-Level Synthesis: It’s Still Hardware Design
By Siemens EDA - 26 May, 2022 - Comments: 0

Hardware design using HLS is no different than the typical ASIC/FPGA design flow with the exception that C++/SystemC is being used along with HLS to create the RTL instead of hand coding it. The advantage of using HLS is that it speeds up RTL creation time and reduces verification time by producing bug free RTL quickly from a fully verified C++/SystemC source. The misconception that still exist... » read more

Incremental Design Breakdown
By Brian Bailey - 24 Mar, 2022 - Comments: 0

For the past two decades, most designs have been incremental in nature. They heavily leveraged IP used in previous designs, and that IP often was developed by third parties. But there are growing problems with that methodology, especially at advanced nodes where back-end issues and the impact of 'shift left' are reducing the savings from reuse. The value of IP reuse has been well established... » read more

Structural Vs. Functional
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

High-Level Synthesis For RISC-V
By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Formally Verifying SystemC/C++ Designs
By Rob van Blommestein - 29 Jul, 2021 - Comments: 0

We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components ... » read more

Dynamically Reconfiguring Logic
By Ed Sperling - 12 Jul, 2021 - Comments: 0

Dynamic reconfiguration of semiconductor logic has been possible for years, but it never caught on commercially. Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, explains why this capability has been so difficult to utilize, what’s changed, how a soft logic layer can be used to control when to read, compute, steer, and write data back to memory, and ... » read more

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