Low Power Trends Toward FinFET

My previous blog, Power Reduction Techniques, covered which low power techniques were applicable for various process nodes, from larger planar CMOS process technologies through finFET. The 16 and 14nm finFET-based process nodes are moving into production this year, and we are seeing many companies rapidly move their designs to finFET. In my last post, I noted some of the reasons why finFET is s... » read more

Implementation Challenges And Solutions Of Low-Power, High-Performance Memory Systems

Mobile devices and their demand for rapid innovation have fundamentally and forever changed the semiconductor industry. These devices have fueled tremendous innovation in the last few years to bring about drastic improvements in performance, power and cost efficiency. They also demand condensed product development cycles which accelerate the rate and need for innovation. The only thing that has... » read more

Choosing The Right Systems Design Path

I’m a cheap bastard, usually given to self-abnegation when it comes to buying material goods for myself. But I broke down and bought a runner’s watch late last year because I wanted to change up my exercise routine to run the same distances, only faster. I quickly decided against going all in and getting a GPS watch. At this point in the arc of electronics-design technology, it’s hard ... » read more

Performance Or Power?

For high-volume chips, such as those slated for mobile devices such as tablets or smart phones, energy efficiency is absolutely critical. For very high-value chips, which are the ones that show up in PCs or servers, the focus is more on performance and how efficiently that performance is obtained. And for the stuff in the middle, notably the Internet of things, the commodity servers and automot... » read more

Experts At The Table: Who Pays For Low Power?

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

Bit Mapping

The rule of thumb for semiconductor manufacturing is that big breakthroughs tend to last a decade, or about five process nodes. While the transistor already has spanned more than five decades and the IC more than four decades, the technology used to create them typically only lasts about one. 193nm lithography has been around more than a decade. Bets were being made publicly back at 45nm—o... » read more

New Issues In Signoff

By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

New Challenges, New Name

As you’ll notice today, we’ve changed our name from Low Power Engineering to Low-Power/High-Performance Engineering. We don’t take name changes lightly—we've been discussing this in depth with readers, sponsors, and researchers for the past six months. The almost universal conclusion is there is a big shift underway in the semiconductor industry today, and our new logo is a better refle... » read more