FinFET Front-End-of-Line (FEOL) Process Integration With SEMulator3D

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology inno... » read more

Near-Threshold Computing

By Bhanu Kapoor There were two main contributing factors to power becoming a big problem ("The Power Wall") starting around the 65nm process technology. First, the fast-growing leakage component became as significant as the dynamic power. Second, the scaling of the supply voltage stopped around 1.1 volts. Process technology advances such as HKMG and 3D tri-gate transistors have enabled con... » read more

The Trouble With FinFETs

By Joanne Itow The industry’s quest to continue on the semiconductor roadmap defined by Moore’s Law has led to the adoption of a new transistor structure. Whether you call them finFETs, tri-gate or 3D transistors, building these new devices is difficult. But the technology is only half the challenge. In 2002, Chen Ming Hu* spoke at the Semico Summit. The title of his presentation was ... » read more

All Indicators Point North

Designing and producing chips has always been difficult, but the number of things that conspire to make it harder at 20nm is the longest in the history of the semiconductor industry. The list will grow longer still at 14nm and beyond, not to mention so expensive that one mistake will kill a company. While system engineers and architects look at the challenges on the front end, the problems ... » read more