Week In Review: Design, Low Power


Design & IP Arm launched the Neoverse Compute Subsystems (CSS), pre-integrated and validated configurations of Arm Neoverse platform IP, at this week's Hot Chips conference. CSS helps streamline SoC designs for data centers and is optimized for an advanced 5nm process. The first generation of CSS (Neoverse CSS N2) is based on Arm’s Neoverse N2 platform. Core count is configurable (24 to ... » read more

Who Will Regulate Data Exchanges In Chiplets?


Scaling is still important when it comes to logic and low power, but it's no longer the main avenue for improving performance. What used to be a single chip, comprised of various IP blocks and components on a single SoC, is giving way to a heterogeneous collection of chiplets — at least for the big chipmakers and system companies at the leading edge. Chiplets are currently the best solutio... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive and mobility U.S. President Joe Biden announced the approval of $900 million in funding for a nationwide network of electrical vehicle charging stations in 35 states. The money is part of a multi-year, $7.5 billion plan to create 500,000 charging stations along federal highways. Industry executives told Reuters that remote human supervisors may be a permanent fixture of highly au... » read more

Will Big Competition Attract More Talent For IC Companies?


Google is hiring a chip packaging technologist. General Motors is seeking a wafer fabrication procurement specialist. Facebook Reality Labs wants a materials researcher with experience in photolithography and nanoimprint techniques. Recent job postings by tech and automotive giants are enough to worry any chip company executive struggling to attract talent. But what may seem at first like a ... » read more

ML Focus Shifting Toward Software


New machine-learning (ML) architectures continue to garner a huge amount of attention as the race continues to provide the most effective acceleration architectures for the cloud and the edge, but attention is starting to shift from the hardware to the software tools. The big question now is whether a software abstraction eventually will win out over hardware details in determining who the f... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs Reports have surfaced that TSMC has delayed its 3nm process. But TSMC says the technology remains on track. Volume production for TSMC’s 3nm is still scheduled for the second half of 2022. On the flip side, there is speculation that TSMC may increase its wafer prices by up to 20%, according to a report from the Taipei Times. Here's another report. This is due to chip shortag... » read more

New Architectures, Much Faster Chips


The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

The Next Leap


Some interesting new technologies are about to go on display. Chipmakers and systems companies have been working on quantum computing, photonics, and specialized AI processors, for the past several years, and those efforts are beginning to gain momentum. The goal is no longer a doubling of performance and power. It's now orders of magnitude improvement, and next week's Hot Chips conference i... » read more

Week In Review: Design, Low Power


Cadence added new machine learning functionality to its Xcelium Logic Simulator to speed verification closure on randomized regressions. Xcelium ML directly interfaces to the simulation kernel and learns iteratively over an entire simulation regression, guiding the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Kioxia adop... » read more

System-in-Package For Heterogeneous Designs


System integration is increasingly being done using 3D packaging technologies rather than integrating everything onto a huge SoC. One motivation is the ability to not just to split up a design in a single process, but to package die from different processes. Sometimes there are economic reasons. Several presentations at HOT CHIPS had a partition of the design into the processor itself, and a... » read more

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