Creating An Accurate FEOL CMP Model


By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows  design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

Design Process Technology Co-Optimization For Manufacturability


Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology... » read more