Manufacturing Bits: Oct. 25


GaN-on-GaN power semis Power semiconductors based on gallium nitride (GaN) are heating up in the market. Typically, suppliers are shipping devices using a GaN-on-silicon process. These devices are available with blocking voltages of up to 650 volts. Going beyond 650 volts is problematic, however. GaN-on-silicon processes suffer from lattice mismatches, cost and other issues. At the ... » read more

Improving Transistor Reliability


One of the more important challenges in reliability testing and simulation is the duty cycle dependence of degradation mechanisms such as negative bias temperature instability ([getkc id="278" kc_name="NBTI"]) and hot carrier injection (HCI). For example, as previously discussed, both the shift due to NBTI and the recovery of baseline behavior are very dependent on device workload. This is ... » read more

Will 5nm Happen?


Chipmakers are ramping up their 16/14nm finFET processes, with 10nm finFETs expected to ship sometime in late 2016 or early 2017. So what’s next? The foundries can see a path to extend the finFET transistor to 7nm, but the next node, 5nm, is far from certain and may never happen. Indeed, there are several technical and economic challenges at 5nm. And even if 5nm happens, only a few compani... » read more

Manufacturing Bits: Dec. 29


Printing hair Using a low-cost, 3D printing technique, Carnegie Mellon University has found a way to produce hair-like strands and fibers. The printer produces plastic hair strand by strand. It takes about 20-25 minutes to generate hair on 10 square millimeters. A video can be seen here. [caption id="attachment_24544" align="alignleft" width="300"] 3D printed hair (Photo: Carnegie Mellon... » read more

Manufacturing Bits: Dec. 15


DRAM scaling sans EUV At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., chipmakers presented papers on several technologies, including one unlikely topic—DRAM scaling. For years, it was believed that DRAMs would hit the wall and stop scaling at 20nm or so. Then, at that point, the industry would need to migrate to a 3D DRAM structure or a next-generatio... » read more

ReRAM Gains Even More Steam


The prospect of using the latest in finFET processing to enable embedded non-volatile memory (NWM) will be described by a team from TSMC and Tsing Hua University in Taiwan at the IEDM meeting on Dec. 8 in Washington, D.C. Embedded NVM has been the first commercial application of ReRam, with products from Panasonic and Terrazon. Industry leaders agree the creation of NVM as a seamless additio... » read more

Technology Reboot Required


The International Technology Roadmap for Semiconductors (ITRS) has produced reports outlining the major obstacles the electronics industry faces for a long time now. It attempts to project, with a 15-year horizon, the problems that need to be solved in order to take advantage of the complete design and manufacturing ecosystem. From this, early research efforts can be started. This enabled the E... » read more

Reliability After Planar Silicon


Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient elec... » read more

How To Deal With Electromigration


The replacement of aluminum with copper interconnect wiring, first demonstrated by IBM in 1997, brought the integrated circuit industry substantial improvements in both resistance to electromigration and line conductivity. Copper is both a better and more stable conductor than aluminum. Difficult though the transition was, it helped extend device scaling for another eighteen years (and counting... » read more

Darker Silicon


For the last several decades, integrated circuit manufacturers have focused their efforts on [getkc id="74" comment="Moore's Law"], increasing transistor density at constant cost. For much of that time, Dennard’s Law also held: As the dimensions of a device go down, so does power consumption. Smaller transistors ran faster, used less power, and cost less. As most readers already know, howe... » read more

← Older posts