The Week In Review: Design


IP Arastu Systems uncorked a LPDDR3 DRAM Memory Controller. The controller is fully compliant with JEDEC standard JESD209-3C and supports various power down modes as well as multiple channels with a privilege to configure and manage each channel independently and parameterized data width. CSEM's Bluetooth Low Energy silicon RF IP has been validated as Bluetooth 5 compatible. RF test equip... » read more

The Week In Review: Design


IP eSilicon launched 14nm FinFET and 28nm planar HBM Gen2 Hardened PHY. It supports up to 256Gbytes/sec bandwidth with 8x128b channels at 2Gbps per I/O, and the integrated I/O supports up to 2Gbps DDR operation across a 4mm interposer channel. The PHY was developed on Samsung 14LPP and TSMC 28HPC technologies. Flex Logix designed a high-performance embedded FPGA IP core for TSMC 16FF+ and... » read more

The Week In Review: Design


M&A Siemens plans to buy Mentor Graphics for $4.5 billion in cash. The move, if approved by regulators, would greatly expand Siemens’ capabilities in multi-physics design and embedded software for everything from semiconductors to automotive wiring harnesses. The transaction is expected to close in the second quarter of 2017. Tools Mentor Graphics uncorked a new product to measur... » read more

The Week In Review: Design


M&A Mentor Graphics acquired Galaxy Semiconductor, a provider of test data analysis and defect reduction software ranging from initial characterization of sample devices to automated yield management of large-scale production. The Galway, Ireland company was founded in 1998. Terms of the deal were not disclosed. IP Imagination rolled out a new heterogeneous MIPS CPU with many core/... » read more

The Week In Review: Design


Numbers EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. IP Cadence launched the latest generation of its Xtensa ... » read more

The Week In Review: Design


M&A Intel will acquire Movidius, adding the company's low-power vision processing unit to its growing computer vision efforts that include a depth-sensing camera and machine learning projects. At the same time, Intel is shedding cybersecurity unit McAfee (acquired in 2011 for $7.7 billion and re-named Intel Security in 2014). Intel will retain a 49% stake in the business with the 51% rem... » read more

The Week In Review: Design


Tools Synopsys unveiled its next-generation ATPG and diagnostics solution, TetraMAX II. According to the company, the tool is an order of magnitude faster than the previous generation, reducing runtime from days to hours, as well as generating 25% fewer patterns. The new tool is also certified for the ISO 26262 automotive functional safety standard. It has been deployed by STMicroelectronics... » read more

The Week In Review: Design


Tools Synopsys unveiled a new HAPS adaptor that enables a HAPS FPGA-based Prototyping System to easily connect to a Juno ARM Development Platform. The software development platform includes the Juno Versatile Express board with ARM Cortex-A72, or Cortex-A57 and Cortex-A53 MPCore, Mali-T624 and reference software through Linaro Linux. Numbers Imagination released financial results for t... » read more

The Week In Review: Design


Tools Synopsys uncorked the latest version of its software for the design of optical communication systems and photonic integrated circuits at the signal propagation level, adding a new interface and expanding the software's application design libraries. Mentor Graphics said it would provide a variety of tools to support the new Zynq UltraScale+ MPSoC devices from Xilinx, dual-core field-... » read more

The Week In Review: Design/IoT


Tools Aldec updated its emulation and simulation acceleration software package for high speed prototyping boards, adding a SCE-MI Pipes-based flow for streaming large amounts of data, and a 30% speed increase for all emulation modes. Plus, Aldec's mixed-language FPGA design and simulation platform now includes a complete coverage analysis package for FPGA and ASIC designers with the addition... » read more

← Older posts