The Week In Review: Design


Tools Mentor released the latest version of its FloTHERM CFD software for electronics cooling simulation, adding a new design window to create and solve variants of a model with features to improve scenario definition and design space exploration. Other enhancements include support for Phase Change Materials, more abilities for PCB designs, and an improved parallel solver. Markets IC Insig... » read more

The Week In Review: Design


Numbers EDA industry revenue increased 10.5% in Q1 2017 to $2.168 billion, the highest Q1 growth level since 2011, according to EDAC. The four quarters moving average increased by 10.6%. CAE, the biggest category, grew 14%, while IP—primarily macro cells and memory—grew 15%. The Americas and Asia-Pacific both reported double digit growth. The industry is hiring, too: tracked companies incr... » read more

The Week In Review: Design


M&A Silvaco will acquire SoC Solutions, adding more IP experience to the company's portfolio. SoC Solutions, based in Atlanta, GA, focuses on pre-configured IP subsystems and IP targeting low power IoT and machine-to-machine communication. Terms of the deal were not disclosed, but the acquisition is expected to close soon. Imagination is putting the rest of the company up for sale after... » read more

The Week In Review: Design


M&A Verific acquired Invionics' entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific. Portable Stimulus An Early Adopter release of the Portable Stimulus specification has been made publicly availabl... » read more

The Week In Review: Design


M&A Consultancy Sondrel acquired IMGworks, formerly the design services unit of Imagination. Sondrel says it plans to focus on design services for ADAS systems, AI, and machine vision and learning devices. Terms of the deal were not disclosed. Tools Cadence expanded its formal verification platform, JasperGold, adding linting and clock domain crossing apps that address RTL signoff ... » read more

The Week In Review: Design


Tools Synopsys debuted a tool to replay RTL simulation data on a gate-level netlist for power analysis the company says is accurate within 5% of signoff. The tool, PowerReplay, is design to be used in combination with PrimeTime PX gate-level power analysis for earlier and faster generation of gate-level switching data. IP ClioSoft launched a design reuse ecosystem for searching and com... » read more

The Week In Review: Design


Imagination has put the MIPS embedded processor and Ensigma mobile connectivity groups up for sale, refocusing on graphics after last month's announcement that Apple would no longer use the company's GPU IP. Imagination also began formal dispute resolution procedures with Apple. Tools Synopsys released new versions of its HSPICE, FineSim and CustomSim circuit simulation products, adding n... » read more

The Week In Review: Design


Name Changes Arteris changed its name to ArterisIP. The company said the name change better reflects what the company does, which is provide IP for SoC communication on-die and between die. Mentor Graphics also modified its name, following last week's announcement that the acquisition by Siemens has been completed. The company is now officially called Mentor, A Siemens Business. It also ... » read more

The Week In Review: Design


IP Arastu Systems uncorked a LPDDR3 DRAM Memory Controller. The controller is fully compliant with JEDEC standard JESD209-3C and supports various power down modes as well as multiple channels with a privilege to configure and manage each channel independently and parameterized data width. CSEM's Bluetooth Low Energy silicon RF IP has been validated as Bluetooth 5 compatible. RF test equip... » read more

The Week In Review: Design


IP eSilicon launched 14nm FinFET and 28nm planar HBM Gen2 Hardened PHY. It supports up to 256Gbytes/sec bandwidth with 8x128b channels at 2Gbps per I/O, and the integrated I/O supports up to 2Gbps DDR operation across a 4mm interposer channel. The PHY was developed on Samsung 14LPP and TSMC 28HPC technologies. Flex Logix designed a high-performance embedded FPGA IP core for TSMC 16FF+ and... » read more

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