Ruthenium Liners Give Way To Ruthenium Lines


For several years now, integrated circuit manufacturers have been investigating alternative barrier layer materials for copper interconnects. As interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. As previously reported, both cobalt and ruthenium have drawn substantial interest because they can serve as both barrier and seed layers, minimizi... » read more

Blog Review: Aug. 16


Cadence's Paul McLellan checks out how Imec sees the future of transistors and the challenges of 3D logic. Synopsys' Robert Vamosi gets a lesson on the electronic systems powering modern cars, and considers when it's ethical to hack one. Mentor's Colin Walls takes a look at how to pass data between RTOS tasks. Rambus' Aharon Etengoff looks at recent semi market predictions, from expand... » read more

Manufacturing Bits: Aug. 8


Ferroelectric films Ferroelectric RAM (FRAM) is creating a buzz again. For years, FRAMs have been shipping for embedded applications, although the technology has taken a backseat to MRAM, phase-change and ReRAM. Using a ferroelectric capacitor to store data, FRAM is a nonvolatile memory with unlimited endurance. FRAM is faster than EEPROM and flash. FRAM performs an over-write function in ... » read more

What’s After FinFETs?


Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

5 Takeaways From Semicon


At the recent Semicon West trade show in San Francisco, there were a multitude of presentations on a number of subjects. The event, sponsored by SEMI, had presentations on the outlook for ICs, equipment and packaging. Clearly, though, the show is much smaller with fewer attendees, as compared to past years. Most of the big companies no longer have booths. Hardly any have press events or med... » read more

Pessimism, Optimism And Neuromorphic Computing


As I’ve been researching this series on neuromorphic computing, I’ve learned that there are two views of the field. One, which I’ll call the “optimist” view, often held by computer scientists and electrical engineers, focuses on the possibilities: self-driving cars. Homes that can learn their owners’ needs. Automated medical assistants. The other, the “pessimist” view, often hel... » read more

NAND Market Hits Speed Bump


Demand for NAND flash memory remains robust due to the onslaught of data in systems, but the overall NAND flash market is stuck in the middle of a challenging period beset by product shortages, supply chain issues and a difficult technology transition. Intel, Micron, Samsung, SK Hynix and the Toshiba/Western Digital duo continue to ship traditional planar NAND in the market, but this technol... » read more

Inside Chip R&D


Semiconductor Engineering sat down to discuss R&D challenges, EUV and other topics with Luc Van den hove, president and chief executive of Imec, an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Clearly, Moore’s Law is slowing down. The traditional process cadence is extending from 2 years to roughly 2.5 to 3 years. Yet, R&D is not slowing down, right? ... » read more

New BEOL/MOL Breakthroughs?


Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Going Vertical?


The topic of transistor scaling has been traditionally covered at SEMICON West in its own right. This year’s event, however, will also explore scaling in 3D, as well as using packaging to accomplish similar objectives. Along with traditional transistor scaling, speakers will tackle design and metrology considerations for scaling the package, and address the economic decisions that inform dens... » read more

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