Manufacturing Of Next-Generation Channel Materials


One of the many challenges for the IC developers is to change the channel material to increase transistor mobility. But what about manufacturing? Can LED-style epitaxy be migrated to high-volume silicon manufacturing? “The use of Ge and InGaAs quantum wells is an extension of the current strained Si strategy," said Aaron Thean, vice president of process technologies and director of the log... » read more

Still Waiting For III-V Chips


For years, chipmakers have been searching for an alternative material to replace traditional silicon in the channel for advanced CMOS devices at 7nm and beyond. There’s a good reason, too: At 7nm, silicon will likely run out of steam in the channel. Until recently, chipmakers were counting on III-V materials for the channels, at least for NFET. Compared to silicon, III-V materials provide ... » read more

New Challenges For Post-Silicon Channel Materials


In order to bring alternative channel materials into the CMOS mainstream, manufacturers need not just individual transistor devices, but fully manufacturable process flows. Work presented at the recent IEEE Electron Device Meeting (Washington, D.C., Dec. 9-11, 2013) showed that substantial work remains to be done on almost all aspects of such a flow. First and most fundamentally, it is diffi... » read more

The List Of Unknowns Grows After Silicon


As discussed earlier in this series, most proposed alternative channel schemes depend on germanium channels for pMOS transistors, and InGaAs channels for nMOS transistors. Of the two materials, InGaAs poses by far the more difficult integration challenges. Germanium has been present in advanced silicon CMOS fabs for several technology generations, having been introduced used in strained silicon... » read more

Germanium wedge-FETs pry away misfit dislocations


Any approach to alternative channel integration must consider the lattice mismatch between silicon and other channel materials. Some schemes, such as IMEC’s selective epitaxy, view the lattice mismatch as an obstacle and look for ways to minimize its effects. This point of view certainly has merit: misfit dislocations do significantly degrade transistor performance. Still, back in 2011 Shu-Ha... » read more