Stacked Die Changes

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Adapt Or Perish: A Unified Theory Of Coherency

Evolution is a natural process and more importantly a relatively slow process that has eventually got us here, capable of perceiving, analyzing, and handling complex tasks. As our environment, society, and surroundings became more complex we learned how to adapt at a brisk and instantaneous manner, in this melting pot of a heterogeneous world. The evidence can be seen in all ages, from the poli... » read more

From Game Theory To The Unified Theory of Coherency

Adam Smith said that the best result comes from everyone in the group doing what is best for himself. But he’s only half right because the best result would come from everyone in the group doing what is best for himself and the group. If you are wondering where you might have heard this before, it was Russell Crowe playing John Nash in the movie “A Beautiful Mind.” John Nash was an Ame... » read more

Next Challenge: Contact Resistance

In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact. Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or conta... » read more

Executive Insight: K. Charles Janac

K. Charles Janac, chairman and CEO of Arteris, sat down with Semiconductor Engineering to talk about what's changing in the automotive market, the impact of big data, and heterogeneous cache coherency. What follows are excerpts of that discussion. SE: What are the big changes you're seeing in semiconductor design? Janac: There are a lot of changes right now. Mobility is slowing down and b... » read more

High-Bandwidth Memory

High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. This white paper explains HBM’s value proposition, and how these five companies make... » read more

7nm Fab Challenges

Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

The First Fully Configurable Cache-Coherent Interconnect Solution For SoCs

The last few decades have seen a massive growth in the number of CPU cores, computing clusters and other IP blocks in a SoC. This massive growth along with the need for complex chip integration has driven the need for sophisticated interconnects. SoC architects have employed a variety of methods from buses to crossbars to handcrafted NoCs with Lego-like blocks with varying degrees of success. T... » read more

An Architecture Synthesis Platform For Rapidly Evolving SoC Designs

Modern System-on-Chip (SoC) architects are faced with a number of serious challenges. First, the number of Semiconductor Intellectual Property (IP) blocks in SoC designs is growing continuously and increasing design complexity. With IP design reuse becoming more common, the mixing and matching of IP components is further compounding design complexity. Second, sophisticated SoC applications are ... » read more

5nm Fab Challenges

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device req... » read more

← Older posts