tag: interconnects

Impact of CMOS Image Sensors Fabrication Processes On The Quality Of Smartphone Pictures
By Technical Paper Link - 06 Jul, 2023 - Comments: 0

A technical paper titled “A Review of the Recent Developments in the Fabrication Processes of CMOS Image Sensors for Smartphones” was published by researchers at Texas A&M University. Abstract: "CMOS Image Sensors are experiencing significant growth due to their capabilities to be integrated in smartphones with refined image quality. One of the major contributions to the growth of ima... » read more

Impacts Of Process Flow, Scaling, And Variability On Interconnect Performance
By Lam Research - 26 Apr, 2023 - Comments: 0

Virtual fabrication is used to evaluate the performance of interconnects (line and via resistance, capacitance, etc.) across pitches compatible with either EUV single exposure or SADP for three different process flows: single damascene, dual damascene, and semi-damascene (subtractive metal etch). The effects of process variation for the three flows are also investigated to determine the relativ... » read more

Chiplet Security Risks Underestimated
By Ann Mutschler - 06 Apr, 2023 - Comments: 0

The semiconductor ecosystem is abuzz with the promise of chiplets, but there is far less attention being paid to security in those chiplets or the heterogeneous systems into which they will be integrated. Disaggregating SoCs into chiplets significantly alters the cybersecurity threat landscape. Unlike a monolithic multi-function chip, which usually is manufactured using the same process tech... » read more

The Race Toward Mixed-Foundry Chiplets
By Ann Mutschler - 23 Mar, 2023 - Comments: 1

Creating chiplets with as much flexibility as possible has captured the imagination of the semiconductor ecosystem, but how heterogeneous integration of chiplets from different foundries will play out remains unclear. Many companies in the semiconductor ecosystem are still figuring out how they will fit into this heterogeneous chiplet world and what issues they will need to solve. While near... » read more

Looking Inside Of Chips
By Ed Sperling - 10 Jan, 2023 - Comments: 0

Shai Cohen, co-founder and CEO of proteanTecs, sat down with Semiconductor Engineering to talk about how to boost reliability and add resiliency into chips and advanced packaging. What follows are excerpts of that conversation. SE: Several years ago, no one was thinking about on-chip monitoring. What's changed? Cohen: Today it is obvious that a solution is needed for optimizing performanc... » read more

Multi-Wavelength, Multimode Communication Scheme For On-Chip and Chip-to-Chip Interconnects
By Technical Paper Link - 02 Jan, 2023 - Comments: 0

A technical paper titled "Multi-dimensional data transmission using inverse-designed silicon photonics and microcombs" was published by researchers at Stanford, Harvard, University of Central Florida, NIST, and others. "Here we demonstrate an integrated multi-dimensional communication scheme that combines wavelength- and mode- multiplexing on a silicon photonic circuit. Using foundry-compati... » read more

Heterogeneous Integration Issues And Developments
By Ed Sperling - 14 Dec, 2022 - Comments: 0

There are a slew of new developments in advanced packaging, from new materials, chiplets, and interconnect schemes, to challenges involving how to physically put chips in a package, metallization, thermal cycling, and parasitics in the interconnect path. Dick Otte, CEO of Promex Industries, talks about how this will change chip design and manufacturing, and how those changes are likely to unfol... » read more

Big Changes In Architectures, Transistors, Materials
By Ed Sperling - 18 Aug, 2022 - Comments: 0

Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

Hybrid Bonding Basics: What Is Hybrid Bonding?
By Jessica Albright - 18 Aug, 2022 - Comments: 2

Hybrid bonding is the key to paving an innovative future in advanced packaging. Hybrid bonding provides a solution that enables higher bandwidth and increased power and signal integrity. As the industry is looking to enhance the performance of final devices through scaling system-level interconnections, hybrid bonding provides the most promising solution with the ability to integrate several di... » read more

Microarchitectural Side-Channel Attacks and Mitigations on the On-Chip Mesh Interconnect
By Technical Paper Link - 11 Aug, 2022 - Comments: 0

This new technical paper titled "Don't Mesh Around: Side-Channel Attacks and Mitigations on Mesh Interconnects" was presented by researchers at University of Illinois at Urbana-Champaign, MIT, and Texas Advanced Computing Center at the USENIX Security Symposium in Boston in August 2022. Abstract: "This paper studies microarchitectural side-channel attacks and mitigations on the on-chip mes... » read more

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