tag: IP integration

Physically Aware NoCs
By Ed Sperling - 06 Mar, 2023 - Comments: 0

More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip out the door. In many of these devices, the network on chip is the glue between various components, but it can take up to 10% to 12% of the total area of the SoC. Andy Nightingale, vice president of product m... » read more

Importance Of Qualifying IP Revisions
By Siddharth Ravikumar - 30 Jan, 2023 - Comments: 0

Design intellectual property (IP) is the fundamental building block of the modern system on chip (SoC). As the scale and complexity of SoCs increases, usage of design IP blocks also increases rapidly, as they enable modularization and re-use of design components. As a result, the usage of design IP has grown rapidly in the past decade. An IP data library consists of many views and formats, w... » read more

Adding Differentiating Value And Reducing IP Integration Time for Your SoC
By Synopsys - 06 Dec, 2022 - Comments: 0

In the most efficient SoC design processes, semiconductor companies design their own, differentiated IP blocks, acquire high-quality third-party IP, configure it in an SoC-optimized way, and integrate all blocks into the SoC infrastructure of clocks, voltage supplies, on-chip buffer memories or registers, and test circuits. The SoC design team defines and drives the SoC-specific implementation ... » read more

Raising IP Integration Up A Level
By Brian Bailey - 27 Oct, 2022 - Comments: 0

An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

Time For FMEDA Reuse?
By Stefano Lorenzini - 07 Jul, 2022 - Comments: 0

How do designers quantify safety in electronic systems? Through one or more tables called Failure Modes, Effects and Diagnostic Analysis – FMEDA. In fact, an FMEDA does not have to be a table; it could be manifested in scripts or some other form, but a table is the easiest way to think of this information. Think of an FMEDA for an IP, as the concept extends easily to a system-on-chip (SoC). T... » read more

Integrating Embedded FPGA Made Easy
By Andy Jaros - 03 Jun, 2021 - Comments: 0

Chip designers have been integrating hard and soft IPs for decades – some being easy to integrate and others much more difficult. But what about eFPGA? It’s a relatively new IP on the IP landscape and according to data from Gartner, the market share of semiconductors with eFPGA is expected to approach $10B in 2023 with greater than 50% compounded annual growth. So, this raises the question ... » read more

An Acquisition To Streamline SoC Integration
By Kurt Shuler - 15 Feb, 2021 - Comments: 0

Late last year Arteris IP closed its acquisition of Magillem assets, bringing together two companies with a single mission: To support integration of systems-on-chip (SoCs) at the interconnect fabric level and the data integration level. The value of joining forces has been appealing for some time. Since the early days of both companies, we’ve been working with mutual customers and integratio... » read more

IP Integration Verification At DVClub Europe
By Saša Stamenković - 30 Jul, 2020 - Comments: 0

Most people involved in pre-silicon verification of digital designs and electronic design automation (EDA) know the folks at Test and Verification Solutions (T&VS – now acquired by Tessolve to offer a full VLSI and test service). Among other things, they organize the Verification Futures (VF) conference in the UK and the DVClub Europe meetings. These are highly technical events, with plen... » read more

Gaps Emerging In System Integration
By Brian Bailey - 29 Jun, 2020 - Comments: 0

The system integration challenge is evolving, but existing tools and methods are not keeping up with the task. New tools and flows are needed to handle global concepts, such as power and thermal, that cannot be dealt with at the block level. As we potentially move into a new era where IP gets delivered as physical pieces of silicon, this lack of an accepted flow will become a stumbling block. ... » read more

Enabling Integration Success Using High-Speed SerDes IP
By Niall Sorensen - 13 Feb, 2020 - Comments: 0

By Niall Sorensen and Malini Narayanammoorthi Internet traffic volumes continue to grow at a breakneck pace, and the demands on SerDes speeds increase accordingly. High-speed SerDes play an integral part of the networking chain and these speed increases are required to support the bandwidth demands of artificial intelligence (AI), Internet of Things (IoT), virtual reality (VR) and many more ... » read more

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