What Goes Wrong With IP


Semiconductor Engineering sat down to talk about the future of IP with Rob Aitken, R&D fellow at [getentity id="22186" comment="ARM"]; Mike Gianfagna, vice president of marketing at [getentity id="22242" e_name="eSilicon"]; Judd Heape, vice president of product applications at Apical; and Bernard Murphy, an independent industry consultant. What follows are excerpts of that discussion, which... » read more

Will The Chip Work?


As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

Will The Chip Work?


IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

Can IP Integration Be Automated?


What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

Who’s Calling The Shots


Throughout the PC era and well into the mobile phone market, it was semiconductor companies that called the shots while OEMs followed their lead and designed systems around chips. That’s no longer the case. A shift has been underway over the past half decade, and continuing even now, to reverse that trend. The OEM — or systems company as it is more commonly called today — now determine... » read more

Architecting For Optimal Interface IP Integration


Semiconductor Engineering sat down to discuss the design and integration of complex interface [getkc id="43" comment="IP"] with Ty Garibay, VP of engineering at Altera; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Saman Sadr, director of analog design at Semtech; and Nav... » read more

IP Market Booms At Advanced Nodes


As [getkc id="81" kc_name="SoC"] design and manufacturing costs rise, system OEMs are wringing as much of that increase as they can from ASIC vendors. The result is that engineering teams on the design and test side are being constrained by budgets at a time when complexity is rising and time-to-market pressures are increasing. At least one segment is benefiting from directly this. Budgetary... » read more

Enabling The Next Mobile Computing Revolution


We’ve come a long way Just think about the ‘mobile computing’ revolution over the last five years – the compute tasks we routinely handle on our mobile phonesdaily, equal those that were only possible to execute using laptops and desktops several years ago. With a direct and uninterrupted power supply from the wall, laptopsand desktops require fan-assisted cooling, a... » read more

Distortion Effects Prevail In RF Design


It’s an exciting time for consumers of wireless devices, but it’s a challenging time for system designers who must design, analyze and verify that all of the components in those wireless devices interoperate. In wireless designs, distortion effects play an important role in the performance of RF circuits, including mixers, low-noise amplifiers (LNAs) and power amplifiers (PAs) and managi... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

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