Analog Migration Equals Redesign


Analog design has never been easy. Engineers can spend their entire careers focused just on phase-locked loops (PLLs), because to get them right the functionality of circuits need to be understood in depth, including how they respond across different process corners and different manufacturing processes. In the finFET era, those challenges have only intensified for analog circuits. Reuse, fo... » read more

Measuring And Analyzing SoC Performance With Verdi Performance Analyzer


SoC performance is a key competitive advantage in the marketplace. The choice and configuration of SoC components—protocol IP and interconnects, is geared towards maximizing overall SoC performance. A case in point is the use of HBM (High Bandwidth Memory) technology and controllers. Currently in its third generation, HBM boasts high-performance while using less power in a substantially small... » read more

How To Build Functional Safety Into Your Design From The Start


The focus on functional safety IP is rapidly growing and we’re seeing this growth not just in automotive but in many other markets including, avionics, medical, industrial and railways, where systems need to efficiently identify and mitigate the occurrences of faults, and where more confidence is required with respect to the design practises employed for the development of IP. Currently, m... » read more

The Power Of De-Integration


The idea that more functionality can be added into a single chip, or even into a single system, is falling out of vogue. For an increasing number of applications, it's no longer considered the best option for boosting performance or lowering power, and it costs too much. Hooman Moshar, vice president of engineering at Broadcom, said in a keynote speech at Mentor's User2User conference this w... » read more

System-Level Power Modeling Takes Root


Power, heat, and their combined effects on aging and reliability, are becoming increasingly critical variables in the design of chips that will be used across a variety of new and existing markets. As more processing moves to edge, where sensors are generating a tsunami of data, there are a number of factors that need to be considered in designs. On one side, power budgets need to reflect th... » read more

Tech Talk: Shrink Vs. Package


Andy Heinig, group manager for system integration at Fraunhofer EAS, talks about the tradeoffs between planar design and advanced packaging, including different types of interposers, chiplets and thermal issues. https://youtu.be/1BDqgCujJno » read more

The Case For Chiplets


Discussion about chiplets is growing as the cost of developing chips at 10/7nm and beyond passes well beyond the capabilities of many chipmakers. Estimates for developing 5nm chips (the equivalent 3nm for TSMC and Samsung) are well into the hundreds of millions of dollars just for the NRE costs alone. Masks costs will be in the double-digit millions of dollars even with EUV. And that's assum... » read more

Understanding NI CompactRIO Scan Mode


The LabVIEW Real-Time Module 8.6 introduced powerful new features for programming CompactRIO hardware that reduce development time and complexity as well as provide tools for monitoring and maintaining CompactRIO applications. This functionality is powered by two technologies in LabVIEW, the NI Scan Engine and the RIO Scan Interface. The NI Scan Engine is a new component of LabVIEW Real-Time th... » read more

The Week In Review: Design


M&A ANSYS finalized its acquisition of OPTIS. Founded in 1989, OPTIS provided software for scientific simulation of light, human vision and physics-based visualization. The acquisition boosts the company's automotive simulation portfolio with radar, lidar and camera simulation. Terms were not disclosed. IP Arm debuted the Cortex-M35P processor. Aimed at IoT applications, the IP combine... » read more

EDA In The Cloud


Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

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