Blog Review: March 22


Cadence's Paul McLellan shares TSMC's plans for 5nm and gate-all-around FET, plus other highlights from last week's Technology Symposium. Mentor's Craig Armenti examines how product development teams can increase efficiency through concurrent schematic design. Synopsys' Jim Ivers warns of the data security and privacy issues posed by a wave of popular connected toys. At Embedded World,... » read more

Patterning Problems Pile Up


Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

Blog Review: March 15


Cadence's Christen Decoin looks back at the changes in design rule checking and asks, with growing design sizes and rule complexity, has DRC run out of steam? Synopsys' Eric Huang provides some background on DisplayPort and its integration with the USB Type-C connector. In his latest video, Mentor's Colin Walls investigates the relationship between the choice of operating system and the p... » read more

The Week In Review: Manufacturing


Fab tools In response to SEMI members and partners, SEMI says it is not organizing Semicon Russia 2017, or any other events in Russia this year. “In light of the current market conditions and SEMI stakeholder concerns, SEMI reached out to members and customers over the last six months to assess how to provide the most value for our community in Russia,” said Laith Altimime, president of SE... » read more

Fractilia: Pattern Roughness Metrology


A new startup has emerged and unveiled a technology that addresses one of the bigger but less understood problems in advanced lithography--pattern roughness. The startup, called Fractilia, is a software-based metrology tool that analyzes the CD-SEM images of pattern roughness on a wafer. Fractilia, a self-funded startup, is led by Chris Mack and Ed Charrier. Mack, known as the gentleman sc... » read more

The Week In Review: Manufacturing


Chipmakers Toshiba’s problems have gone from bad to worse. “Toshiba postponed its earnings call by up to one month, and the chairman resigned. The provisional results show large losses in its nuclear power business, while the NAND operations remain very profitable,” said Weston Twigg, an analyst with Pacific Crest Securities, in a research note. “The next few months appear very uncerta... » read more

Battling Fab Cycle Times


The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Betting On Wafer-Level Fan-Outs


Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die. The inclusion of a [getkc id="202" kc_name="fan-out"] package for logic in Apple's iPhone 7, based on TSMC's Integrated Fan-Out (... » read more

Blog Review: Feb. 1


Synopsys' Anand Thiruvengadam investigates the challenges and tradeoffs that come with different abstraction models and use models in mixed-signal verification. Cadence's Paul McLellan highlights 16 big questions facing autonomous cars, from a presentation by Andreessen-Horowitz's Frank Chen. Mentor's Colin Walls says that when it comes to free stuff, keep an eye out for the real cost. ... » read more

BEOL Issues At 10nm And 7nm


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

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