Blog Review: Nov. 30


Cadence's Paul McLellan presents a three-part series on the future of EDA, with insights from both academia and industry. Mentor's Harry Foster focuses on power management trends in ASIC design, in the latest installment of the 2016 Wilson Research Group verification study. Plus, what aspects of power are verified and how designers describe power intent. Synopsys' Robert Vamosi reports th... » read more

Why EUV Is So Difficult


For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding. More recently, though, [gettech id="31045" comment="EUV"] lithography appears to be inching closer to pos... » read more

Blog Review: Nov. 16


Cadence's Paul McLellan highlights a talk from the recent Jasper User Group by ARM's Daryl Stewart on how the company saw the value of formal verification. Synopsys' Patrick Sheridan looks at the benefits of using SystemC TLM-2.0 AT for virtual prototype architecture modeling. Mentor's Jim Martens argues for the importance of a reliable power delivery network. A Lam Research staff writ... » read more

The Week In Review: Manufacturing


Chipmakers At upcoming the 2016 IEEE International Electron Devices Meeting (IEDM) in San Francisco, TSMC will square off against the alliance of IBM, GlobalFoundries and Samsung at 7nm. IEDM will take place Dec. 3-7, 2016. TSMC will present a paper on 7nm finFET technology. Using 193nm immersion and multi-patterning, the 7nm technology features more than three times the gate density and ei... » read more

Will There Be Enough Silicon Wafers?


The silicon wafer industry, a critical part of the IC supply chain, is undergoing a new and perhaps alarming wave of merger and acquisition activity. While consolidation in this sector is not new, the pace of M&A activity is picking up and there are fewer companies left. Silicon wafer makers produce and sell raw silicon wafers to chipmakers, which process them into chips. But despite con... » read more

What Happened To Inverse Lithography?


Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications. Today, though, ILT is getting new attention as the semiconductor industry pushes toward 7nm, and perhaps beyond. ILT is not a next-generation ... » read more

The Week In Review: Manufacturing


Fab tools and materials After a series of delays due to regulatory issues, Lam Research and KLA-Tencor have agreed to terminate their proposed merger agreement. Amid a possible proxy battle, Kulicke & Soffa Industries has named Fusen Chen as president and chief executive, effective Oct. 31. He was also elected to the board of K&S. Jonathan Chou, chief financial officer and interim CEO, w... » read more

Blog Review: Oct. 5


Mentor's Michael White explores why established nodes are experiencing such an unexpectedly long lifespan and how that is driving new challenges for designers. Cadence's Ann Keffer checks out the history of Ethernet and how it won the battle to become the dominant network protocol. Is your IoT device fueling a botnet? Vulnerable firmware on internet connected devices was behind one of the... » read more

450mm And Other Emergency Measures


Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

Mask Maker Worries Grow


Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

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