7nm Lithography Choices


Chipmakers are ramping up their 16nm/14nm logic processes, with 10nm expected to move into early production later this year. Barring a major breakthrough in lithography, chipmakers are using today’s 193nm immersion and multiple patterning for both 16/14nm and 10nm. Now, chipmakers are focusing on the lithography options for 7nm. For this, they hope to use a combination of two technologies ... » read more

Double Patterning Custom Design And Debug


Litho-Etch-Litho-Etch (LELE) double pattern (DP) processing affects many aspects of the design flow at/below the 20 nm node level. This can be very disruptive for the custom designer, impacting basic cell design strategy, layout rules and debug as well as parasitic extraction. This paper discusses how to deal with these impacts, avoid common design mistakes, and debug quickly and accurately. ... » read more

Self-Aligned Double Patterning, Part One


I’m sure most of you have seen a Rorschach test ink blot (Figure 1). Psychiatrists ask the subjects to tell them what they “see” in the ink blot. The answers are used to characterize the respondent’s personality and emotional functioning. I am never sure if I would feel more uncertain being the psychiatrist asking the question, or the subject trying to decide what to say, given there ar... » read more