Chipmakers Look Beyond Scaling


Gary Patton, CTO of GlobalFoundries, sat down with Semiconductor Engineering to discuss the rollout of EUV, the rising cost of designing chips at the most advanced nodes, and the growing popularity of 22nm planar FD-SOI in a number of markets. What follows are excerpts of that conversation. SE: You've just begun deploying EUV. Are you experiencing any issues? Patton: It's a very complicat... » read more

Tech Talk: MCU Memory Options


David Eggleston, vice president of embedded memory at GlobalFoundries, talks about the pros and cons of embedded non-volatile memory versus system in package. https://youtu.be/6KoQTFbFVCo » read more

Higher Performance, Lower Power Everywhere


The future of technology is all about information—not just data—at our fingertips, anywhere and at any time. But making all of this work properly will require massive improvements in both performance and power efficiency. There are several distinct pieces to this picture. One is architectural, which is possibly the simplest to understand, the most technologically challenging to realize, ... » read more

Alchip Minimizes Dynamic Power For High-Performance Computing ASICs


Alchip, a fabless ASIC provider, focuses on high-performance computing ASICs. They decided to undertake a new project where they would employ the PowerPro RTL Low-Power Platform to reduce dynamic power consumption within their unique fishbone clock tree methodology. Could they achieve better power results using PowerPro and could they integrate the tool within their team and the existing design... » read more

Designing 5G Chips


5G is the wireless technology of the future, and it’s coming fast. The technology boasts very high-speed data transfer rates, much lower latency than 4G LTE, and the ability to handle significantly higher densities of devices per cell site. In short, it is the best technology for the massive amount of data that will be generated by sensors in cars, IoT devices, and a growing list of next-g... » read more

What Happened To UPF?


Two years ago there was a lot of excitement, both within the industry and the standards communities, about rapid advancements that were being made around low-power design, languages and methodologies. Since then, everything has gone quiet. What happened? At the time, it was reported that the [gettech id="31043" comment="IEEE 1801"] committee was the largest active committee within the IEEE. ... » read more

Spark Microsystems: LP On-Chip Radios


Spark Microsystems is taking aim at on-chip radios that continue to be the primary source of battery drain, even in power-conserving designs like Bluetooth Low Energy. "If you wear AirPods, something like 80% of the power is going to power the radio, not the sound. That's not the most efficient approach." according to Frederic Nabki, co-founder of Spark Microsystems, and a former professor o... » read more

How To Choose The Right Memory


When it comes to designing memory, there is no such thing as one size fits all. And given the long list of memory types and usage scenarios, system architects must be absolutely clear on the system requirements for their application. A first decision is whether or not to put the memory on the logic die as part of the SoC, or keep it as off-chip memory. "The tradeoff between latency and th... » read more

How The Brain Saves Energy By Doing Less


One of the arguments for neuromorphic computing is the efficiency of the human brain relative to conventional computers. By looking at how the brain works, this argument contends, we can design systems that accomplish more with less power. However, as Mireille Conrad and others at the University of Geneva pointed out in work presented at December's IEEE Electron Device Meeting, the brain... » read more

Why Inductance Is Good for Area, Power and Performance


By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

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