Body Bias: What It Is, And Why You Should Care


In case you hadn’t noticed, the use of integrated circuits (ICs) has exploded over the past decade. From the cheapest novelty toy to automobiles to implanted medical devices, it seems like everything we touch has an electronic component in it somewhere. Not surprisingly, that growth has brought with it a vastly expanded number and variety of IC design requirements that design companies must s... » read more

Automated Body Bias Validation For High Performance, Low Power Electronics


Using a device’s body bias effect allows designers to tune a circuit’s behavior to meet both power and performance specifications, but getting it right isn’t always easy. Accurate, fast, automated body bias verification is critical to ensure today’s complex designs meet demanding performance, reliability, and power usage specifications. To read more, click here. » read more

Synthesis Of Energy-Efficient FSMs Implemented In PLD Circuits


The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous ci... » read more

Tech Talk: 7nm Thermal Effects


ANSYS' Karthik Srinivasan talks about the effect of heat on reliability at advanced process nodes, including self-heating, circuit aging, and how that will affect automotive electronics. https://youtu.be/SS6iAXp0Kn8   Related Tech Talk: 7nm Power Dealing with thermal effects, electromigration and other issues at the most advanced nodes. » read more

What Does “Low Power Optimization” Mean To You?


As I was researching some new low power capabilities, I asked this question of nearly every designer I met: “How important is low power optimization?” It turns out that it’s a pretty useless question because of course it’s important to just about everyone. After all, reducing power improves reliability and reduces design costs. And for chips destined for certain applications, such as mo... » read more

Tech Talk: Neural Networks


Megha Daga, senior technical marketing manager at Cadence, talks with Semiconductor Engineering about convolutional neural networks, including the bandwidth and compute challenges associated with them. » read more

Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Performance-IP: Less Memory Latency


The combination of more functionality on chips plus more contention for memories is forcing companies to look at different ways to improve performance. Just adding more processing power doesn't guarantee improved performance, and throwing more memory at a problem—either SRAM or multiple levels of cache—is expensive and not always faster. There are too many processors and too many request... » read more

Cloud Computing Chips Changing


An explosion in cloud services is making chip design for the server market more challenging, more diverse, and much more competitive. Unlike datacenter number crunching of the past, the cloud addresses a broad range of applications and data types. So while a server chip architecture may work well for one application, it may not be the optimal choice for another. And the more those tasks beco... » read more

Power Management Validation


Power consumption is becoming a critical aspect of hardware design. No longer is verifying an SoC solely answering the question “does it work?” Now designers must also answer the question “does it meet my power budget?” When trying to find power issues it is critical to run the complete system in a realistic manner—at the system-level when the design/verification team is looking at th... » read more

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