Near-Threshold Issues Deepen


Complex issues stemming from near-threshold computing, where the operating voltage and threshold voltage are very close together, are becoming more common at each new node. In fact, there are reports that the top five mobile chip companies, all with chips at 10/7nm, have had performance failures traced back to process variation and timing issues. Once a rather esoteric design technique, near... » read more

Tech Talk: 7/5/3nm Signoff


Anand Raman, director of technical marketing at Helic, explains what's needed to improve confidence in designs at the most advanced process nodes. https://youtu.be/2O2pbMJSta4 » read more

Why Inductance Is Good for Area, Power and Performance


By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

Tech Talk: On-Chip Variation


Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. https://youtu.be/LQnw_3H9soQ » read more

Tech Talk: 7nm Process Variation


Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

Trimming Waste In Chips


Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

Worst-Case Results Causing Problems


The ability of design tools to identify worst-case scenarios has allowed many chipmakers to flag potential issues well ahead of tapeout, but as process geometries shrink that approach is beginning to create its own set of issues. This is particularly true at 16/14nm and below, where extra circuitry can slow performance, boost the amount of power required to drive signals over longer, thinne... » read more

What Can Be Cut From A Design?


A long-standing approach of throwing everything into a chip increasingly is being replaced by a focus on what can be left out it. This shift is happening at every level, from the initial design to implementation. After years of trying to fill every square nanometer of real estate on a piece of silicon with memory and logic, doubling the number of [getkc id="26" kc_name="transistors"] from on... » read more

Tech Talk: Power Signoff


Ansys' Aveek Sarkar the challenges of power signoff at advanced process nodes, the impact of over-design, and what's necessary for sufficient coverage. [youtube vid=VQoT2KYW-AM] » read more

Optimization Challenges For 10nm And 7nm


Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

← Older posts