Optimization Challenges For 10nm And 7nm

Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

Big Data Meets Chip Design

The amount of data being handled in chip design is growing significantly at each new node, prompting chipmakers to begin using some of the same concepts, technologies and algorithms used in data centers at companies such as Google, Facebook and GE. While the total data sizes in chip design are still relatively small compared with cloud operations—terabytes per year versus petabytes and exa... » read more

Tech Talk: Power Signoff

Ansys' Aveek Sarkar the challenges of power signoff at advanced process nodes, the impact of over-design, and what's necessary for sufficient coverage. [youtube vid=VQoT2KYW-AM] » read more

Have Margins Outlived Their Usefulness?

To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution which we continuously refine over time. Additionally, we have managed the interdependencies between tasks by defining boundaries or margins; these often have been best- and worst-case values used t... » read more

One On One: John Lee

John Lee, general manager and vice president of Ansys—and the former CEO of data analytics firm Gear Design Solutions, which Ansys acquired in September—sat down with Semiconductor Engineering to talk about how big data techniques can be used in semiconductor and system design. What follows are excerpts of that conversation. SE: What's your goal now that Gear has been acquired by [getent... » read more

New Approaches To Low Power Design

While Moore's Law continues to drive feature size reduction and complexity, a whole separate part of the industry is growing up around vertical markets in the IoT. While these two worlds may be different in many respects, they share one thing in common—low power design is critical to success. How engineering teams minimize power in each of these markets, and even within the same market, ca... » read more

Power Grid Analysis

By Marko Chew Introduction Power grids (PGs) have consumed an increasingly larger percentage of routing resources in recent process node generations, due to lower maximum current limits imposed by the foundry. It is not uncommon to see upwards of 30% of the routing resources consumed by the PG, with correspondingly negative implications for a design’s routability. Of course, the design’... » read more

Experts At The Table: The Growing Signoff Headache

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

Margin Of Error

By Ed Sperling Adding extra circuits and silicon area to a chip has always been frowned upon by chipmakers. Extra silicon means extra money, and for most chips the least expensive is always the better choice. But at advanced process nodes, margin also can slow performance, increase power consumption, and make it harder to achieve timing closure. The obvious solution is to reduce margin thro... » read more