Analyzing Data Differently


Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across a long simulation cycle is very hard to visualize on the waveform. Whenever I have to analyze a huge chunk of data, I always wonde... » read more

ROI Not There Yet For SysML


At some point down the road in the realm of system-level design, the Systems Modeling Language (SysML) dialect of the Unified Modeling Language (UML) standard may drive into semiconductor design. So far, however, a return on investment has not been established for its use. SysML is defined as a general-purpose visual modeling language for systems engineering applications, and it supports the... » read more

Verification As A Deterrent?


By Ed Sperling Verification is becoming more than a bottleneck in semiconductor design. It’s actually deterring companies from adopting the latest techniques for saving power or building certain features into chips. The problem is one of complexity, and it’s getting worse at every node. While the tools exist to do complex designs, there are the classic tradeoffs of area, power and per... » read more