Power/Performance Bits: Oct. 18

Speeding up memory with T-rays Scientists at the Moscow Institute of Physics and Technology (MIPT), the University of Regensburg in Germany, Radboud University Nijmegen in the Netherlands, and Moscow Technological University proposed a way to improve the performance of memory through using T-waves, or terahertz radiation, as a means of resetting memory cells. This process is several thousand... » read more

The Week In Review: Design

M&A Mentor Graphics acquired Galaxy Semiconductor, a provider of test data analysis and defect reduction software ranging from initial characterization of sample devices to automated yield management of large-scale production. The Galway, Ireland company was founded in 1998. Terms of the deal were not disclosed. IP Imagination rolled out a new heterogeneous MIPS CPU with many core/... » read more

Addressing Memory Characterization Capacity And Throughput Requirements With Dynamic Partitioning

Typical memory characterization techniques using memory compilers and instance-specific memories have a number of tradeoffs—development time, accuracy, performance, and more. Ad-hoc instance-specific characterization methods such as dynamic simulation, transistor-level static timing analysis, and divide-and-conquer suffer from multiple limitations that prohibit usage for 40nm technologies and... » read more

In An Election Year: OTP For IoT

Borrowing from this year’s hottest topic –– the Presidential Election –– let’s nominate one-time programmable (OTP) embedded memory for the Internet of Things (IoT). It’s sure to be the winner for any number of reasons, but most likely it is because of its built-in security features. As a memory-on-chip technology, antifuse OTP is paving the way for IoT designers to come up with n... » read more

Reduced Memory Power For Internet of Things Applications

Memory has historically been a very stable technology, whether volatile or non-volatile. Incremental change happens constantly to improve performance, but it’s unusual for a major change to take place. The non-volatile one-time-programmable memory approach that Kilopass uses has been in place for thirteen years with no major changes. Now, however, Kilopass is readying a new memory array for t... » read more

Designers: Take Control Of Your Chip

This is a familiar story for us – maybe it is for you, too. From time to time, a customer contacts us and says they have a design in mind, but they just can’t fit in the package, or meet the power budget, or meet timing. Fifty percent or more of the area for many of the chips we see is composed of memory. So we start there. After a Pareto analysis of the memory sub-system, we typically find... » read more

Sorting Out Next-Gen Memory

In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. [getkc id="92" kc_name="SRAM"], the first tier of this hierarchy, is... » read more

Executive Insight: Sundari Mitra

Sundari Mitra, co-founder and CEO of [getentity id="22535" e_name="NetSpeed Systems"], sat down with Semiconductor Engineering to discuss machine learning, shifting from a processor-centric to a memory-centric design, and what needs to change to make that all happen. What follows are excerpts of that conversation. SE: What is the biggest change you’re seeing? Mitra: We go through a cycl... » read more

Implementing ESD Protection In Today’s SoCs

As the semiconductor industry transitions to FinFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts. Technology ... » read more

The Week In Review: Design

Memory Nantero licensed its technology for non-volatile RAM using carbon nanotubes (NRAM) to Fujitsu Semiconductor and Mie Fujitsu Semiconductor, which plan to conduct joint development towards releasing a product based on 55-nm process technology. Fujitsu Semiconductor plans to develop an NRAM-embedded custom LSI product by the end of 2018. IP Flex Logix completed design of a family o... » read more

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