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Digging Deep Into High Aspect Ratio Process Control For Memory Technology


By Mark Shirey and Janay Camp Data is an integral part of our lives. Contrary to the past, where files had to be removed periodically to free up storage space, we now assume that our data will never be deleted. Why risk deleting the wrong file? Just keep them! This new approach consumes a lot of memory, and intensifies the demand for storage. Two of the main workhorses of the memory segment ... » read more

Blog Review: Oct. 17


Arm's Shidhartha Das explores the challenges of power delivery in designing mobile systems and the importance of focusing on peak power consumption. Synopsys' Meenakshy Ramachandran explains the basics of Display Stream Compression and how it works to increase the effective bandwidth enabling support of high resolution displays. Cadence's Paul McLellan shares tips on more effective market... » read more

Making AI Run Faster


The semiconductor industry has woken up to the fact that heterogeneous computing is the way forward and that inferencing will require more than a GPU or a CPU. The numbers being bandied about by the 30 or so companies working on this problem are 100X improvements in performance. But how to get there isn't so simple. It requires four major changes, as well as some other architectural shifts. ... » read more

Blog Review: Oct. 10


In a video, Cadence's Megha Daga dives into sparsity in neural networks and how it affects bandwidth, performance, and power efficiency. In a video, Mentor's Colin Walls takes a look at efficient embedded code, and why that means different things at different times. Synopsys' Eric Huang argues that in the realm of video standards, HDMI, DisplayPort, and USB Type-C are set to continue comp... » read more

The Next Big Chip Companies


Rambus’ Mike Noonen looks at why putting everything on a single die no longer works, what comes after Moore’s Law, and what the new business model looks like for chipmakers. https://youtu.be/X6Kca8Vm-wA » read more

Hybrid Memory


Gary Bronner, senior vice president of Rambus Labs, talks about the future of DRAM scaling, why one type of memory won’t solve all needs, and what the pros and cons are of different memories. https://youtu.be/R0hhDx2Fb7Q » read more

Intel’s Next Move


Gadi Singer, vice president and general manager of Intel's Artificial Intelligence Products Group, sat down with Semiconductor Engineering to talk about Intel's vision for deep learning and why the company is looking well beyond the x86 architecture and one-chip solutions. SE: What's changing on the processor side? Singer: The biggest change is the addition of deep learning and neural ne... » read more

A Primer On Last-Level Cache Memory For SoC Designs


System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver assistance systems (ADAS), machine learning, and data-center applications. LLC is a standalone memory that inserts cache between functional blocks and external memory to ease conflicting requireme... » read more

Energy-Efficient AI


Carlos Maciàn, senior director of innovation for eSilicon EMEA, talks about how to improve the efficiency of AI operations by focusing on the individual operations, including data transport, computation and memory. https://youtu.be/A3p_w7ENefs » read more

Carbon Nanotube DRAM


An IP design house has developed a scalable DRAM replacement using carbon nanotubes (CNTs) that abolishes the DRAM refresh rate, stores the content permanently, has better timing than DRAM and is scalable. And it lasts for somewhere between 300 and 12,000 years. “Carbon nanotube memory—it sounds so sexy that I could just shut up and not say anything,” said Bill Gervasi, principal syste... » read more

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