System Performance Analysis At ARM


Performance analysis is a vital task in modern SoC design. An under-designed SoC may run too slowly to keep up with the demands of the system. An over-designed SoC will consume too much power and require more expensive IP blocks. At ARM we want to help our partners build SoCs that deliver the best performance within their power and area budgets. The simple truth is that this is more difficul... » read more

And The Award Goes To…


I like to look at what users find the most interesting topics, not because it directly influences what I write, but to get a sense of the subjects that are on most people's minds. Some of it comes as no surprise. Content about new fabrication technologies tends to blow everything else away. While it directly affects very few of us, I think we all want to know the general direction of the indust... » read more

Executive Insight: Charlie Cheng


[getperson id="11073" comment="Charlie Cheng"], CEO of [getentity id="22135" e_name="Kilopass Technology"], sat down with Semiconductor Engineering to talk about the limitations of DRAM, how to get around them, and who's likely to do that. What follows are excerpts of that discussion. SE: What are the top market segments from a [getkc id="22" kc_name="memory"] standpoint? Cheng: The top o... » read more

IP Market: CPU Still The Largest But Security Leads In Growth


The 3rd Party Semiconductor Intellectual Property (SIP) market has seen great innovation in the products it offers to System-on-a-Chip (SoC) designers over the last ten years. If any market segment in the semiconductor industry typifies the intense evolutionary pressures that the entire electronics market has undergone, it is the 3rd Party SIP market. Most of these evolutionary forces are dr... » read more

Power/Performance Bits: Oct. 18


Speeding up memory with T-rays Scientists at the Moscow Institute of Physics and Technology (MIPT), the University of Regensburg in Germany, Radboud University Nijmegen in the Netherlands, and Moscow Technological University proposed a way to improve the performance of memory through using T-waves, or terahertz radiation, as a means of resetting memory cells. This process is several thousand... » read more

The Week In Review: Design


M&A Mentor Graphics acquired Galaxy Semiconductor, a provider of test data analysis and defect reduction software ranging from initial characterization of sample devices to automated yield management of large-scale production. The Galway, Ireland company was founded in 1998. Terms of the deal were not disclosed. IP Imagination rolled out a new heterogeneous MIPS CPU with many core/... » read more

Addressing Memory Characterization Capacity And Throughput Requirements With Dynamic Partitioning


Typical memory characterization techniques using memory compilers and instance-specific memories have a number of tradeoffs—development time, accuracy, performance, and more. Ad-hoc instance-specific characterization methods such as dynamic simulation, transistor-level static timing analysis, and divide-and-conquer suffer from multiple limitations that prohibit usage for 40nm technologies and... » read more

In An Election Year: OTP For IoT


Borrowing from this year’s hottest topic –– the Presidential Election –– let’s nominate one-time programmable (OTP) embedded memory for the Internet of Things (IoT). It’s sure to be the winner for any number of reasons, but most likely it is because of its built-in security features. As a memory-on-chip technology, antifuse OTP is paving the way for IoT designers to come up with n... » read more

Reduced Memory Power For Internet of Things Applications


Memory has historically been a very stable technology, whether volatile or non-volatile. Incremental change happens constantly to improve performance, but it’s unusual for a major change to take place. The non-volatile one-time-programmable memory approach that Kilopass uses has been in place for thirteen years with no major changes. Now, however, Kilopass is readying a new memory array for t... » read more

Designers: Take Control Of Your Chip


This is a familiar story for us – maybe it is for you, too. From time to time, a customer contacts us and says they have a design in mind, but they just can’t fit in the package, or meet the power budget, or meet timing. Fifty percent or more of the area for many of the chips we see is composed of memory. So we start there. After a Pareto analysis of the memory sub-system, we typically find... » read more

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