Custom Chip Verification Issues Grow


With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom. As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including... » read more

Blog Review: March 29


In a video, Cadence's Megha Daga introduces how convolutional neural networks identify objects and the wide range of applications for the technology. Mentor's Ron Press proposes a way to take advantage of hierarchical DFT features, even if a design wasn't designed for it. Synopsys' Robert Vamosi shares highlights of the RAND Corporation's extensive report examining zero day vulnerabilitie... » read more

Supporting CPUs Plus FPGAs


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

The Week In Review: Design


Tools Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow. Space Codesign introduced the latest version of its simulation environmen... » read more

IoT Edge Design Demands A New Approach


A new breed of designers has arrived that is leveraging the advances in sensing technology to build the intelligent systems at the edge of the IoT. These systems play in every space: on your body, at home, the car or bus that you take to work, and the cities, factories, office buildings, or farms that you work. The energy that you consume and how you travel, by air, land, or sea, all have IoT e... » read more

The CEO Outlook Returns


One of the more popular events hosted by the EDA Consortium (EDAC, to those in the know) was the CEO Forecast held at the start of each year. It was phased out several years ago for a number of reasons, including logistics and scheduling. Attendance was never one of them. As I took the reins of EDAC two years ago, I repeatedly heard how much that evening was missed. Members and non-members h... » read more

Rapid SoC Proof-Of-Concept For Zero Cost


A new breed of designers has arrived that is leveraging inexpensive sensors to build the intelligent systems at the edge of the Internet of Things (IoT). They work in small teams, collaborate online, and they expect affordable design tools that are easy to use in order to quickly produce results. Their goal is to deliver a functioning device to their stakeholders while spending as little money ... » read more

Data Leakage And The IIoT


The Internet of Things has raised concerns about people hacking into home networks or using armies of bots to disrupt communications. But with the Industrial IoT, the stakes are significantly higher—and the effects can last much longer. Security tops the list of concerns as more industrial equipment is connected to the Internet, according to numerous industry insiders. That hasn't stopped ... » read more

Blog Review: March 22


Cadence's Paul McLellan shares TSMC's plans for 5nm and gate-all-around FET, plus other highlights from last week's Technology Symposium. Mentor's Craig Armenti examines how product development teams can increase efficiency through concurrent schematic design. Synopsys' Jim Ivers warns of the data security and privacy issues posed by a wave of popular connected toys. At Embedded World,... » read more

Patterning Problems Pile Up


Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

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