Gaps In The Verification Flow

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

The Week In Review: Design

Tools Mentor Graphics added RF verification capabilities for wireless applications in the connected sensor and IoT markets to its Tanner design and layout suite. Mentor also integrated its Questa verification tool with the open-source Jenkins Continuous Integration and Source Code Management (CI/SCM) ecosystem. The plugin, a free download, gives Jenkins the ability to utilize regression run ... » read more

Creating An Accurate FEOL CMP Model

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows  design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

What Happened To Inverse Lithography?

Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications. Today, though, ILT is getting new attention as the semiconductor industry pushes toward 7nm, and perhaps beyond. ILT is not a next-generation ... » read more

2.5D Surprises And Alternatives

Semiconductor Engineering sat to discuss advanced packaging issues with Juan Rey, senior director of engineering for Calibre at [getentity id="22017" e_name="Mentor Graphics"]; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; and Lisa Minwell, [getentity id="22242" e_name="eSilicon's"] senior director of IP marketing. What follows are excerpts of that conversation. ... » read more

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

Blog Review: Oct. 19

Mentor's Colin Walls provides some tips on writing portable, reusable code. Cadence's Christine Young contends that you should never use 2.5D for characterization at advanced nodes. Synopsys' Eric Huang considers one impractical use of USB heating and the IoT. Applied's Ben Lee predicts a rapid growth in China's power device manufacturing. NXP's Joppe Bos digs into the challenges of... » read more

Side-Channel Attacks Make Devices Vulnerable

As the world begins to take security more seriously, it becomes evident that a device is only as secure as its weakest component. No device can be made secure by protecting against a single kind of attack. Hypervisors add a layer of separation between tasks making sure that one task cannot steal secrets from another. Protection of the JTAG port is necessary to prevent access underneath the h... » read more

The Week In Review: IoT

Memory Kilopass Technology uncorked its new eNVM, which includes vertical layered thyristor DRAM technology. The key advantages, according to the company, is that it eliminates the need for DRAM refresh, can be manufactured using existing processes, and improves power and area efficiency. A full memory test chip is currently in the early stages of testing. A thyristor is basically a latch tech... » read more

The Week In Review: Design

M&A Mentor Graphics acquired Galaxy Semiconductor, a provider of test data analysis and defect reduction software ranging from initial characterization of sample devices to automated yield management of large-scale production. The Galway, Ireland company was founded in 1998. Terms of the deal were not disclosed. IP Imagination rolled out a new heterogeneous MIPS CPU with many core/... » read more

← Older posts