Challenges Grow For IP Reuse


As chip complexity increases, so does the complexity of IP blocks being developed for those designs. That is making it much more difficult to re-use IP from one design to the next, or even to integrate new IP into an SoC. What is changing is the perception that standard [getkc id="43" kc_name="IP"] works the same in every design. Moreover, well-developed [getkc id="100" kc_name="methodologie... » read more

Why Auto Designs Take So Long


Designing chips for the automotive market is adding significant overhead, particularly for chips with stringent safety requirements. On the verification side it could result in an additional 6 to 12 months of work. On the design side, developing the same processor in the mobile market would take 6 fewer man months. And when it comes to complex electronic control units (ECUs) or [getkc id="81... » read more

Spec-Driven Design


Anupam Bakshi, CEO of Agnisys, sat down with Semiconductor Engineering to discuss problems in the design flow and what needs to be fixed. What follows are excerpts of that conversation. SE: What are the big problems facing the industry? Bakshi: There is a disconnect from the specification down to the implementation. That's why verification has become so big. Specification down to implemen... » read more

Formal Confusion


Semiconductor Engineering sat down to discuss the right and wrong ways to apply formal verification technology with Normando Montecillo, associate technical director at [getentity id="22649" comment="Broadcom"]; Ashish Darbari, principal engineer at [getentity id="22709" e_name="Imagination Technologies"]; Roger Sabbagh, principal engineer at Huawei; and Stuart Hoad, lead engineer at PMC Sierra... » read more

ESL Flow is Dead


It was 20 years ago that Gary Smith coined the term [getkc id="48" comment="Electronic System Level"] (ESL). He foresaw the next logical migration in abstraction up from the [getkc id="49" comment="Register Transfer Level"] (RTL) to something that would be capable of describing and building complex electronic systems. He also saw that the future of EDA depended upon who would control that marke... » read more

Power — Usage Shift Leads to Methodology Shift


Power exploration and accurate power calculation of SoCs in the target application environment is getting executive attention due to the fact that companies are missing market windows because of power issues. This makes system-level power analysis and management a key measurement. Verification solutions that provide accurate power analysis data early are critical to making design decisions that... » read more

Developing Effective Design Strategies For Today’s Wearable Devices: Security


We love our wearables, but wearable devices connected to public networks supporting bi-directional data flow make our devices...and us...highly susceptible to attack. Security can no longer be thought of as an “afterthought” to embedded system design; development teams must design in security methods and adopt a security development lifecycle approach that meets the appropriate security lev... » read more

The Ultimate Shift Left


Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several semiconductor development teams, especially those in Fortune 500 companies, who do not have time to change their design process. They often cite various reasons such as: • Too busy with the current project. • What we have is working, so... » read more

Education And Communication


With the System Development Suite introduced back in 2011, it is worthwhile to review how the adoption of the connected verification engines has progressed. It turns out that only part of the issues to be solved are purely technical. Communication across different technology areas is key, and with that, education of a new breed of engineer may become a key issue going forward. As a son of a ... » read more

Will The Chip Work?


As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

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