tag: micro-architectures

RISC-V Micro-Architectural Verification
By Brian Bailey - 21 Dec, 2023 - Comments: 3

RISC-V processors are garnering a lot of attention due to their flexibility and extensibility, but without an efficient and effective verification strategy, buggy implementations may lead to industry problems. Prior to RISC-V, processor verification almost became a lost art for most semiconductor companies. Expertise was condensed into the few commercial companies that provided processors or... » read more

Customizing Processors
By Brian Bailey - 28 Jul, 2022 - Comments: 1

The design, verification, and implementation of a processor is the core competence of some companies, but others just want to whip up a small processor as quickly and cheaply as possible. What tools and options exist? Processors range from very small, simple cores that are deeply embedded into products to those operating at the highest possible clock speeds and throughputs in data centers. I... » read more

Preparing For 3D-ICs
By Ed Sperling - 16 Feb, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

More Data Drives Focus On IC Energy Efficiency
By Ann Mutschler - 08 Apr, 2021 - Comments: 0

Computing workloads are becoming increasingly interdependent, raising the complexity level for chip architects as they work out exactly where that computing should be done and how to optimize it for shrinking energy margins. At a fundamental level, there is now more data to compute and more urgency in getting results. This situation has forced a rethinking of how much data should be moved, w... » read more

Micro-Architectural Exploration for Low Power Design
By Abhishek Ranjan - 14 Jan, 2016 - Comments: 0

In the first part of this series, we had discussed the need to perform power optimizations and exploration at higher levels of abstractions where the potential to reduce the power consumption is highest. We presented the need for making coarser changes at higher level of abstractions to exploit full power saving potential. In the second part, we discussed some very potent micro-architectural te... » read more

Signal And Power Integrity Cross Paths
By Ed Sperling - 05 Dec, 2014 - Comments: 2

Signal integrity and power integrity historically have been relatively independent issues, and engineers with expertise in one area generally operate independently of the other. But as more power domains are added to conserve energy and allow more features, as voltages are reduced to save battery life, and as dynamic power becomes more of a concern at advanced nodes, these worlds are suddenly m... » read more

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