The Week In Review: Design


Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

Get Ready For Nanotube RAM


The memory market is going in several different directions at once. On one front, the traditional memory types, such DRAM and flash, remain the workhorse technologies in systems despite undergoing some changes in the business. Then, several vendors are readying the next-generation memory types in the market. As part of an ongoing series, Semiconductor Engineering will explore where the new a... » read more

The Week In Review: Design


Memory Nantero licensed its technology for non-volatile RAM using carbon nanotubes (NRAM) to Fujitsu Semiconductor and Mie Fujitsu Semiconductor, which plan to conduct joint development towards releasing a product based on 55-nm process technology. Fujitsu Semiconductor plans to develop an NRAM-embedded custom LSI product by the end of 2018. IP Flex Logix completed design of a family o... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions Cadence acquired [getentity id="22444" comment="Rocketick"], an Israel-based company focused on multicore parallel simulation. Founded in 2008, their original rise and claim to fame was acceleration on GPUs, having received significant funding from Nvidia. The deal is expected to close in the second quarter of fiscal 2016, and terms were not disclosed. Tools &am... » read more