tag: Mimasic

Power Panel: IP And Other Key Issues For Future Development
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed. Prapanna Tiwari: UPF and CPF are text files that capture the power i... » read more

Power Panel: IP And Other Key Issues For Future Development
By Ed Sperling - 10 Feb, 2011 - Comments: 0

Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed. Bhanu Kapoor: There are two components of power—dynamic and leakage. Dynamic is wh... » read more

Tough Road Ahead For Small IP Vendors
By Bhanu Kapoor - 10 Feb, 2011 - Comments: 0

By Bhanu Kapoor The IP business is a difficult one. The vendors who typically supply to larger semiconductor companies face thin margins and different IP requirements to be supported across their customer base. On top of that, no one wants an IP that has not been proven in the field. But if you are looking to be an IP supplier for a low-power SoC that will be manufactured in leading edge p... » read more

Getting Real About Power Management Verification
By Bhanu Kapoor - 02 Dec, 2010 - Comments: 0

By Bhanu Kapoor SoCs that are used in consumer electronics utilize power management techniques that require control of voltage sources. We have discussed the need for power-aware simulation for verification purposes in the past. EDA tools have advanced to include power-aware simulation such as those found with simulators like VCS from Synopsys. In this article, we discuss the need for modeling... » read more

The Value Of Adaptive Body Biasing
By Bhanu Kapoor - 07 Oct, 2010 - Comments: 0

By Bhanu Kapoor Although the use of power gating techniques is essential to manage standby leakage power, it brings in a host of new design and verification issues. This list of new design and verification issues includes putting together a power switch network, incorporating appropriate isolation and retention, addressing x-propagation, dealing with current spikes, and ensuring retention work... » read more

Challenges In Creating Power-Managed IP
By Bhanu Kapoor - 09 Sep, 2010 - Comments: 0

By Bhanu Kapoor Creating low power IPs worked fairly well—at least until the process technology nodes for which leakage power wasn’t a big issue and clock gating was able to address dynamic power optimization. For 90nm and more advanced process technology nodes, leakage power became a dominant issue and the dynamic power needed better optimization. The use of voltage-based power management... » read more

Why So Formal?
By Bhanu Kapoor - 21 May, 2010 - Comments: 0

By Bhanu Kapoor Let’s take a look at the types of power management verification issues that are most suited for formal verification and how formal techniques complement dynamic simulation-based verification in some of the challenging tasks associated with validating SoC power management architectures. There are three main categories of formal tools in use today: Equivalence Checkers, Asse... » read more

Killer Bugs
By Ed Sperling - 08 Apr, 2010 - Comments: 0

By Ed Sperling Hardware and software bugs are all around us. When an application suddenly dies or a smart phone freezes because of the unanticipated interaction between hardware and software blocks in a system on chip, most users aren’t even the least bit fazed. They usually just re-boot and forget about it. Bugs caused by power are an entirely different matter, however. For one thing, ... » read more

Slow and Steady Wins The (Low-Power) Race
By Bhanu Kapoor - 08 Apr, 2010 - Comments: 0

By Bhanu Kapoor Power is a key reason behind the shift in processor design to leverage multi-core architectures because it promises increase in performance without a proportional increase in energy consumption. For an application developer, today’s processors—microprocessors, as well as embedded system processors such as cell phone application processors and wireless sensor network n... » read more

Experts At The Table: Low-Power Management And Verification
By Ed Sperling - 19 Mar, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, corporate applications engineer at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed. Prapanna Tiwari: Traditional techniques like clock-gating an... » read more

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