Tech Talk: 5/3nm Parasitics

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. » read more

Signal Integrity Methodology For Double-Digit Multi-Gigabit Interfaces

As data rates for serial link interfaces such as PCI Express (PCIe) Gen 4 move into the double digits, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream... » read more

Preparing For Electromagnetic Crosstalk Challenges

By Magdy Abadir and Anand Raman Electromagnetic (EM) coupling/noise is not a new phenomenon, but increasing bandwidth and decreasing size, along with low-power demands of today’s electronic systems is making EM crosstalk a first order challenge. At clock frequency of 10GHz+ and data rate of 10Gbps+, parasitic inductance and inductive coupling that were previously safe to ignore are no long... » read more

Co-modeling: A Powerful Capability For Hardware Emulation

Understanding co-modeling technology, its impact on verification and validation should be a critical aim for anyone selecting and deploying emulation co-modeling resources. This paper explores how emulation co-modeling — specifically for the Veloce Strato emulation platform from Mentor, a Siemens business — is architected to meet the needs of advanced verification and validation. To rea... » read more

Reducing BEOL Parasitic Capacitance Using Air Gaps

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have b... » read more

Verifying AI, Machine Learning

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down to talk about artificial intelligence, machine learning, and neuromorphic chips. What follows are excerpts of that conversation. SE: What's changing in [getkc id="305" kc_name="machine learning"]? Brinkmann: There’s a real push toward computing at the edge. ... » read more

SerDes Signal Integrity Challenges At 28Gbps And Beyond

After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV). With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization... » read more

What Is Portable Stimulus?

When [getentity id="22028" e_name="Accellera"] first formed the [getentity id="22863" comment="Portable Stimulus Working Group”] and gave it that name, I was highly concerned. I expressed my frustration that the name, while fitting with what most people thought [getkc id="10" kc_name="verification"] is about, does not reflect the true nature of the standard being worked on. In short, it is no... » read more

The Ultimate Shift Left

Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

Power-Aware Analysis Solution

By reviewing the classic (or traditional) SI methodology, analyzing high-speed design flow, and examining what is employed in Cadence Sigrity power and signal simulations using the SPEED2000, PowerSI, Transistor-to-Behavioral Model Conversion (T2BTM), and SystemSI tools, this paper explains how a general power-aware SI solution not only should be capable of performing SSN simulations, but also ... » read more

← Older posts