Simulating Composite Structures


Composites provide new solutions for manufacturers looking for stronger, lighter and more cost-effective materials. At the same time, they pose new modeling and manufacturing challenges because of the nature of the materials. With the right simulation tools, designers can account for residual stresses, predict performance, analyze reliability and potential failures, optimize construction, and e... » read more

Optimization Challenges For 10nm And 7nm


Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032" e... » read more

Context Is Everything


With consumer and industrial IoT applications, the importance of system context to IC vendors is paramount. No more are the days of developing a chip in isolation; close partnership with systems companies is de rigueur as they provide the use case data that is foundational to development of systems that work. While this makes sense in a smartphone, it’s significantly harder to achieve in a... » read more

Reaching The Power Budget


Everything related to power in chip design today is a big deal—and it’s just getting bigger. Meeting the power budget is becoming harder at each new node, but it's also becoming difficult in a number of new application areas at existing nodes. That's a big problem because [getkc id="108" kc_name="power"] is now considered a competitive advantage in many markets. It's also one of the most... » read more

Pattern Dependence Process Modeling


First order process modeling can help tremendously with process setup and integration challenges that occur in a semiconductor fabrication flow, by visualizing process variation problems “virtually” prior to actual fabrication. In some instances, a deeper level of complexity needs to be added to the process model to capture the effects of variation in the process. Specific examples inclu... » read more

System-Level Verification Tackles New Role


Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

The Week In Review: IoT


Taiwan’s annual Computex trade show, celebrating its 35th anniversary this year, opened this week, and the Internet of Things is among the focus areas of the exhibition. Tsai Ing-wen, the new president of Taiwan, said at the opening ceremony, “The IoT era is coming strong. Taiwan must focus on the integration of hardware and software along with low-volume, high-variety manufacturing capabil... » read more

Cooperation Instead Of Competition


I spent more than 20 years working in EDA and managed to do so without ever working for one of the big three. Big EDA companies were always the competition. Oh sure, you’d partner with them strategically if you could, but always keeping in mind that little fish swimming with big fish often end up being eaten. That all changed seven months ago when ARM acquired Carbon’s technology and tea... » read more

Foundation IP For 7nm FinFETs: Design And Implementation


Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive model... » read more

New Memory Approaches And Issues


New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

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