How Small Will Transistors Go?

By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

Pathfinding Beyond FinFETs

Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from E... » read more

The Trouble With MEMS

The advent of the Internet of Things will open up a slew of new opportunities for MEMS-based sensors, but chipmakers are proceeding cautiously. There are a number of reasons for that restraint. Microelectromechanical systems are difficult to design, manufacture and test, which initially fueled optimism in the MEMS ecosystem that this market would command the same kinds of premiums that analo... » read more

Will 5nm Happen?

Chipmakers are ramping up their 16/14nm finFET processes, with 10nm finFETs expected to ship sometime in late 2016 or early 2017. So what’s next? The foundries can see a path to extend the finFET transistor to 7nm, but the next node, 5nm, is far from certain and may never happen. Indeed, there are several technical and economic challenges at 5nm. And even if 5nm happens, only a few compani... » read more

Memory Choices Grow

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization. There are plenty of rules ... » read more

Why Packaging Matters

The semiconductor package is changing. What was until very recently considered an afterthought is now becoming a key part of the design process at all major chipmakers, and a critical factor in the extension of Moore's Law. This is a sharp reversal of what was almost universally an afterthought in planar silicon design and manufacturing. Rarely was the package an integral part of the archite... » read more

Is HW Or SW Running the Show?

In the past, hardware was designed and then passed over to the software team for them to add their contribution to the product. This worked when the amount of software content was small and the practice did not significantly contribute to product delays. Over time, the software content grew and today it is generally accepted that software accounts for more product expense than hardware, takes l... » read more

Electronics Butterfly Effect

Everyone has heard of the butterfly effect where a small change in a non-linear system can result in large difference in an outcome. For the past 40 years, the electronics industry has approximated a linear system, fed primarily by Moore’s Law. The incremental changes available at each new process node have led us to make incremental changes and improvements in many aspects of the design, its... » read more

Manufacturing And Packaging Changes For 2015

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

One-On-One: Aaron Thean

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

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