MTJ-based Circuits Provide Low-Cost, Energy Efficient Solution For Future Hardware Implementation in SC Algorithms


A review paper titled "Review of Magnetic Tunnel Junctions for Stochastic Computing" was published by researchers at University of Minnesota Twin Cities. Funding agencies include Semiconductor Research Corporation (SRC), CAPSL, NIST, DARPA and others. Abstract: "Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as... » read more

High Performance Memory: Novel Lateral Double Magnetic Tunnel Junction (MTJ) With An Orthogonal Polarizer


A new technical paper titled "Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory" was published by researchers at Hanyang University. Find the technical paper here. Published November 2022. Sin, S., Oh, S. Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory.... » read more

Edge-AI Hardware for Extended Reality


New technical paper titled "Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications" from researchers at Indian Institute of Technology Delhi and Reality Labs Research, Meta. Abstract "Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse. In this work, we investigate two representative XR w... » read more

3 Emerging Technologies: Memristors, Spintronics & 2D Materials


New technical paper titled "Memristive, Spintronic, and 2D-Materials-Based Devices to Improve and Complement Computing Hardware" from researchers at University College London and University of Cambridge. Abstract "In a data-driven economy, virtually all industries benefit from advances in information technology—powerful computing systems are critically important for rapid technological pr... » read more

SOT-MRAM-based CIM architecture for a CNN model


New research paper "In-Memory Computing Architecture for a Convolutional Neural Network Based on Spin Orbit Torque MRAM", from National Taiwan University, Feng Chia University, Chung Yuan Christian University. Abstract "Recently, numerous studies have investigated computing in-memory (CIM) architectures for neural networks to overcome memory bottlenecks. Because of its low delay, high energ... » read more

CXL and OMI: Competing or Complementary?


System designers are looking at any ideas they can find to increase memory bandwidth and capacity, focusing on everything from improvements in memory to new types of memory. But higher-level architectural changes can help to fulfill both needs, even as memory types are abstracted away from CPUs. Two new protocols are helping to make this possible, CXL and OMI. But there is a looming question... » read more

A crossbar array of magnetoresistive memory devices for in-memory computing


Samsung has demonstrated the world’s first in-memory computing technology based on MRAM. Samsung has a paper on the subject in Nature. This paper showcases Samsung’s effort to merge memory and system semiconductors for next-generation artificial intelligence (AI) chips. Abstract "Implementations of artificial neural networks that borrow analogue techniques could potentially offer low-po... » read more

SOT-MRAM To Challenge SRAM


In an era of new non-volatile memory (NVM) technologies, yet another variation is poised to join the competition — a new version of MRAM called spin-orbit torque, or SOT-MRAM. What makes this one particularly interesting is the possibility that someday it could supplant SRAM arrays in systems-on-chip (SoCs) and other integrated circuits. The key advantages of SOT-MRAM technology are the pr... » read more

Outlook: DRAM, NAND, Next-Gen Memory


Jim Handy, director at Objective Analysis, sat down with Semiconductor Engineering to talk about the 3D NAND, DRAM and next-generation memory markets. What follows are excerpts of that discussion. SE: How would you characterize the NAND market thus far in 2021? Handy: All chips are seeing unusual strength in 2021, but NAND flash and DRAM are doing what they usually do by exhibiting more e... » read more

More Errors, More Correction in Memories


As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

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