5nm Fab Challenges


At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device req... » read more

Speeding Up E-beam Inspection


Wafer inspection, the science of finding killer defects in chips, is reaching a critical juncture. Optical inspection, the workhorse technology in the fab, is being stretched to the limit at advanced nodes. And e-beam inspection can find tiny defects, but it remains slow in terms of throughput. So to fill the gap, the industry has been working on a new class of multiple beam e-beam inspectio... » read more

Next EUV Challenge: Mask Inspection


Extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography is still not ready for prime time, but the technology finally is moving in the right direction. The EUV light source, for example, is making progress after years of delays and setbacks. Now, amid a possible breakthrough in EUV, the industry is revisiting a nagging issue and asking a simple question: How do you inspect EUV p... » read more

5 Disruptive Mask Technologies


Photomask complexity and costs are increasing at each node, thereby creating a number of challenges on several fronts. On one front, for example, traditional single-beam e-beam tools are struggling to keep up with mask complexity. As a result, the write times and costs continue to rise. Mask complexity also impacts the other parts of the tool flow, such as inspection, metrology and repair. I... » read more