tag: nanowire

Red MicroLEDs Three Orders of Magnitude Smaller in Surface Area
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "N-polar InGaN/GaN nanowires: overcoming the efficiency cliff of red-emitting micro-LEDs" was published by researchers at University of Michigan. The researchers created "red-microLEDs that are nearly three orders of magnitude smaller in surface area than previously reported devices while exhibiting external quantum efficiency of ~1.2%," according to the University o... » read more

Variation Threat In Advanced Nodes, Packages Grows
By Ed Sperling - 21 Dec, 2020 - Comments: 0

Variation is becoming a much bigger and more complex problem for chipmakers as they push to the next process nodes or into increasingly dense advanced packages, raising concerns about the functionality and reliability of individual devices, and even entire systems. In the past, almost all concerns about variation focused on the manufacturing process. What printed on a piece of silicon didn't... » read more

Challenges At 3/2nm
By Ed Sperling - 15 Sep, 2020 - Comments: 0

David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

Power/Performance Bits: March 31
By Jesse Allen - 31 Mar, 2020 - Comments: 0

Tellurium transistors Researchers from Purdue University, Washington University in St Louis, University of Texas at Dallas, and Michigan Technological University propose the rare earth element tellurium as a potential material for ultra-small transistors. Encapsulated in a nanotube made of boron nitride, tellurium helps build a field-effect transistor with a diameter of two nanometers. �... » read more

Manufacturing Bits: Jan. 2
By Mark LaPedus - 02 Jan, 2019 - Comments: 0

Better nanowire MOSFETs At the recent IEEE International Electron Devices Meeting (IEDM), Imec and Applied Materials presented a paper on a new and improved way to fabricate vertically stacked gate-all-around MOSFETs. More specifically, Imec and Applied reported on process improvements for a silicon nanowire MOSFET, which is integrated in a CMOS dual work function metal replacement metal ga... » read more

Inside Chip R&D
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss R&D challenges, EUV and other topics with Luc Van den hove, president and chief executive of Imec, an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Clearly, Moore’s Law is slowing down. The traditional process cadence is extending from 2 years to roughly 2.5 to 3 years. Yet, R&D is not slowing down, right? ... » read more

2.5D, ASICs Extend to 7nm
By Mark LaPedus - 13 Jun, 2017 - Comments: 2

The leading-edge foundry market is heating up. For example, GlobalFoundries, Intel, Samsung and TSMC have recently announced their new and respective processes. The new processes from vendors range anywhere from 10nm to 4nm, although the current battle is taking place at 10nm and/or 7nm. In fact, one vendor, GlobalFoundries, this week will describe more details about its previously-announced... » read more

How Small Will Transistors Go?
By Mark LaPedus - 18 Aug, 2016 - Comments: 1

By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

Manufacturing Bits: Feb. 17
By Mark LaPedus - 17 Feb, 2015 - Comments: 0

Swedish nano Sweden’s Lund University plans to build a pilot production facility for startups in the field of nanotechnology. The facility would be used for Swedish companies and researchers to build products. This is for companies who do not have the funds to build their own facilities or buy expensive equipment. The project originates from the successful research into nanowires at Lund ... » read more

One-On-One: Aaron Thean
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

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