Device Pin-Specific Property Extraction For Layout Simulation


As we work through the sub-20 nm design space, the interactions between and effects on devices that are near each other are becoming critical factors in achieving the desired electrical performance. Accurate extraction of device pin-specific properties for modelling these effects is essential to attaining design goals. LVS extraction challenges Layout vs. schematic (LVS) comparison tools prov... » read more

The Week In Review: Manufacturing


Is Moore’s Law alive or dead? That’s still a topic for debate. In any case, chipmakers continue to move to advanced nodes, but the transitions are taking longer. Even mighty Intel is struggling, based on what the company said about its 14nm finFET process during an investors meeting this week. In fact, Intel continues to struggle with its yields. “14nm yield is maturing; 14nm is still not... » read more