Speeding Up Neural Networks


Neural networking is gaining traction as the best way of collecting and moving critical data from the physical world and processing it in the digital world. Now the question is how to speed up this whole process. But it isn't a straightforward engineering challenge. Neural networking itself is in a state of almost constant flux and development, which makes it something of a moving target. Th... » read more

The Week In Review: Design


IP Arastu Systems uncorked a LPDDR3 DRAM Memory Controller. The controller is fully compliant with JEDEC standard JESD209-3C and supports various power down modes as well as multiple channels with a privilege to configure and manage each channel independently and parameterized data width. CSEM's Bluetooth Low Energy silicon RF IP has been validated as Bluetooth 5 compatible. RF test equip... » read more

Adapt Or Perish: A Unified Theory Of Coherency


Evolution is a natural process and more importantly a relatively slow process that has eventually got us here, capable of perceiving, analyzing, and handling complex tasks. As our environment, society, and surroundings became more complex we learned how to adapt at a brisk and instantaneous manner, in this melting pot of a heterogeneous world. The evidence can be seen in all ages, from the poli... » read more

Leading Chip Maker Rolls Out SoC For Automotive Market With NetSpeed Gemini


While SoC performance is important to support automotive applications, three criteria, safety, security, and reliability have to outperform almost any other application. Safety because an automobile is a life-critical system, security because you don’t want to allow any malware to penetrate this system, and finally reliability as we all expect our car to be failure-free for years if not decad... » read more

Racing To Design Chips Faster


A shift is underway to develop chips for more narrowly defined market segments, and in much smaller production runs. Rather than focusing on shrinking features and reducing cost per transistor by the billions of units, the emphasis behind this shift is less about scale and much more about optimization for specific markets and delivering those solutions more quickly. As automotive, consumer e... » read more

The Week In Review: Design/IoT


Imec and Cadence completed the first tapeout of a 5nm test chip. Using a processor design, the companies taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning. Tools Synopsys folded in recent acquisition Atrenta's testabilit... » read more