Executive Insight: Sundari Mitra

Sundari Mitra, co-founder and CEO of [getentity id="22535" e_name="NetSpeed Systems"], sat down with Semiconductor Engineering to discuss machine learning, shifting from a processor-centric to a memory-centric design, and what needs to change to make that all happen. What follows are excerpts of that conversation. SE: What is the biggest change you’re seeing? Mitra: We go through a cycl... » read more

Adapt Or Perish: A Unified Theory Of Coherency

Evolution is a natural process and more importantly a relatively slow process that has eventually got us here, capable of perceiving, analyzing, and handling complex tasks. As our environment, society, and surroundings became more complex we learned how to adapt at a brisk and instantaneous manner, in this melting pot of a heterogeneous world. The evidence can be seen in all ages, from the poli... » read more

Top Mobile OEM Uses NetSpeed to Boost Its Next Gen Application Processor

The smartphone segment is certainly the most competitive market for chip makers today and the yearly product launch cadence puts a lot of pressure on the application processor design cycle. End-users expect to benefit from higher image definition, better sound quality, ever faster and more complex applications which push the limits of application processor performance in terms of higher frequen... » read more

Automating Front-End SoC Design With NetSpeed’s On-Chip-Network IP

This white paper from The Linley Group examines the challenges of turning SoC architecture specifications into successful design implementations. It presents the case that SoCs are becoming too large and complex for existing design methodologies and identifies the need for a more automated front-end design process. To read more, click here. » read more

Optimizing Enterprise-Class SSD Host Controller Design With Arteris FlexNoC Network-On-Chip Interconnect IP

Solid state storage is rapidly supplanting rotary storage in data center computing, driven by the competing needs for lower power consumption, lower latency and higher bandwidth. But the inherent unreliability of flash cells mandates the use of sophisticated host controllers to guarantee data reliability and endurance for enterprise solid state disks (SSD). Leading enterprise SSD companies have... » read more

Top 5 Reasons The SoC Interconnect Matters

The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

NoC Versus PIN: Size Matters

Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC archi... » read more

Don’t Forget To Consider Productivity In Semiconductor IP Evaluations

When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment Tool to aid in assessing the value of IP (there is also a quality assessment tool). This aid is part of the G... » read more

Lightweight Cryptography For The IoE

This is the age where technology is expected to do more, faster, anonymously, and often invisibly. And it's supposed to use less power, with smaller footprints, unobtrusively and intuitively. And all that needs to be protected with cryptography. That's the goal, at least. But as Simon Blake-Wilson, vice president of products and marketing for [getentity id="22671" e_name="Rambus"]' Cryptogra... » read more

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency

Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here's why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency. SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher... » read more

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