FD-SOI Strains For The Future


One of the challenges facing supporters of FD-SOI is the need to provide a pathway to improved performance. While FD-SOI wafers offer some significant advantages over bulk silicon wafers, performance enhancements like strain and alternative channel materials are more difficult to implement in the thin SOI environment. On the other hand, once a fab is willing to incorporate layer transfer techni... » read more

E-beam Vs. Optical Inspection


The wafer inspection business is heating up as chipmakers encounter new and tiny killer defects in advanced devices. Last month ASML Holding entered into an agreement to acquire Hermes Microvision (HMI), the world’s largest e-beam inspection vendor, for $3.1 billion. The proposed move propelled ASML into the e-beam wafer inspection market. In addition, [getentity id="22817" e_name="Appl... » read more

2.5D Becomes A Reality


Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

7nm Fab Challenges


Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

Internet of FD-SOI Things?


Are fully-depleted silicon-on-insulator (FD-SOI) wafers having a moment? Certainly SOI wafers are not new. Soitec’s SmartCut layer transfer technology was patented in 1994, and wafers with implanted oxide layers were available before that. Still, adoption of SOI wafers has been limited. Though they offer improved device isolation and reduced parasitics, the increased wafer cost has been an ob... » read more

The End Of Silicon?


As transistors shrink, not all device parameters scale at the same rate—and therein lies a potentially huge problem. In recent years, manufacturers have been able to reduce equivalent oxide thickness (EOT) more quickly than operating voltage. As a result, the electric field present in the channel and gate dielectric has been increasing. Moreover, EOT reduction is achieved in part by reduci... » read more

Still Waiting For III-V Chips


For years, chipmakers have been searching for an alternative material to replace traditional silicon in the channel for advanced CMOS devices at 7nm and beyond. There’s a good reason, too: At 7nm, silicon will likely run out of steam in the channel. Until recently, chipmakers were counting on III-V materials for the channels, at least for NFET. Compared to silicon, III-V materials provide ... » read more

Next Channel Materials?


Chipmakers are making a giant leap from planar transistors to [getkc id="185" kc_name="finFETs"]. Initially, [getentity id="22846" e_name="Intel"] moved into finFET production at 22nm and is now ramping up its second-generation finFETs at 14nm. And the other foundries will enter the finFET fray at 16nm/14nm. So what’s next? Chipmakers will likely extend the finFET architecture to both 10nm... » read more

Transistor Options Narrow For 7nm


Chipmakers are currently ramping up silicon-based finFETs at the 16nm/14nm node, with plans to scale the same technology to 10nm. Now, the industry is focusing on the transistor options for 7nm and beyond. At one time, the leading contenders involved several next-generation transistor types. At present, the industry is narrowing down the options and one technology is taking a surprising lea... » read more

Experts At The Table: Process Technology Challenges


By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more

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