Cache Coherency In Heterogeneous Systems


Until recently, coherency was something normally associated with DRAM. But as chip designs become increasingly heterogeneous, incorporating more and different types of compute elements, it becomes harder to maintain coherency in that data without taking a significant hit on performance and power. The basic problem is that not all compute elements fetch and share data at the same speed, and syst... » read more

Automotive Semiconductor March Madness 2024


As the US is amid "Basketball March Madness" – hard to ignore when you live in Silicon Valley – it also felt like the month of "Automotive Madness." We saw numerous announcements and events across the design chain, from semiconductor IP to software and IP providers to automotive OEMs. And in all of them, data-transport architectures, and with that networks-on-chips (NoCs), are critical. Ma... » read more

Interconnects Essential To Heterogeneous Integration


Designing and manufacturing interconnects is becoming more complex, and more critical to device reliability, as the chip industry shifts from monolithic planar dies to collections of chips and chiplets in a package. What was once as simple as laying down a copper trace has evolved into tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even junctions for optical ... » read more

NoC Development – Make Or Buy?


In the selection and qualification process for semiconductor IP, design teams often consider the cost of in-house development. Network-on-Chip (NoC) IP is no different. In “When Does My SoC Design Need A NoC?” Michael Frank and I argued that most of today’s designs – even less complex ones – can benefit from NoCs. In the blog “Balancing Memory And Coherence: Navigating Modern Chip A... » read more

AI Accelerator Architectures Poised For Big Changes


AI is driving a frenzy of activity in the chip world as companies across the semiconductor ecosystem race to include AI in their product lineup. The challenge now is how to make AI run faster, use less energy, and to be able to leverage it from the edge to the data center — particularly with the rollout of large language models. On the hardware side, there are two main approaches for accel... » read more

SoC Integration And Data Transport Architecture Requirements Surge In 2023


As the holiday season is in full swing, it's retrospection and prediction time! Let's look at what I thought 2023 would look like, review how it turned out, and take a first stab at 2024 predictions. As a spoiler, my biggest surprise was the intensity with which artificial intelligence and machine learning (AI/ML) accelerated since Generative AI was put on the mainstream adoption map last year,... » read more

An Entangled Heterarchy


For decades, a form of structural hierarchy has been the principal means of handling complexity in chip design. It's not always perfect, and there is no ideal way in which to divide and conquer because that would need to focus on the analysis being performed. In fact, most systems can be viewed from a variety of different hierarchies, equally correct, and together forming a heterarchy. The e... » read more

A Survey Of Recent Advances And Research Activities In Wireless NoC Security


A technical paper titled “Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures” was published by researchers at Macquarie University (Sydney). Abstract: "Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-performance multicore computing and network system architectures. Its adoption has become widespread due to t... » read more

Network-on-Chips Enabling Artificial Intelligence/Machine Learning Everywhere


Recently, I attended the AI HW Summit in Santa Clara and Autosens in Brussels. Artificial intelligence and machine learning (AI/ML) were critical themes for both events, albeit from different angles. While AI/ML as a buzzword is very popular these days in all its good and bad ways, in discussions with customers and prospects, it became clear that we need to be precise in defining what type of A... » read more

IBM’s Energy-Efficient NorthPole AI Unit


At this point it is well known that from an energy efficiency standpoint, the biggest bang for the back is to be found at the highest levels of abstraction. Fitting the right architecture to the task at hand i.e., an application specific architecture, will lead to benefits that are hard or impossible to claw back later in the design and implementation flow.  With the huge increase in the inter... » read more

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